ADC12DJ3200: About ADC code error

Hi Toshiyuki

The ADC12DJ3200 ADC uses a unified folding interpolating architecture. This architecture provides very high sample rates, and very low code error rate. The code error rate is much lower than the pipeline architecture used in the ADS54J54.

Unfortunately the DDC features included in the ADC12DJ3200 are not available in the single-input interleaved mode of operation where 6 GSPS can be achieved.

Please refer to section 7.3.6 of the ADC12DJ3200 datasheet. In dual input mode where the DDC features are available the ADC can sample as high as 3.2GSPS.

The DDC decimation factors available are listed in Table 11. The data flow and architecture is shown in Figure 67.

The available modes are:

• No decimation
• Decimate-by-2 - Real output - High Pass or Low Pass response
• Decimate-by-4 - Complex output - (80% alias protected bandwidth)
• Decimate-by-4 - Complex output - (87.5% alias protected bandwidth, reduced stop-band attenuation)
• Decimate-by-8 - Complex output - (80% alias protected bandwidth)
  
• Decimate-by-16 - Complex output - (80% alias protected bandwidth)
  

All of the complex output decimation modes also include a complex mixing stage which allows frequency shifting of the desired signal band prior to decimation.

The real output decimate-by-2 mode only supports High Pass or Low Pass response but might provide what the customer needs with similar output bandwidth to 6 GSPS and decimation by 4.

I hope this is helpful.

Best regards,

Jim B