ADS7042: ADS7042

Hi Jade

Please see below my answers to your question

Case1) AVDD PMIC_3.3V / DVDD 1.8V
ADC input analog signal could be power on/off during normal operation.
Need to check, ADC input pin leakage voltage from AVDD when input signal power off case.

Case2) AVDD GNSS_3.3V / DVDD 1.8V
GNSS_3.3V could be power on/off during normal operation due to connected another block power reset.

Case3) AVDD 1.8V / DVDD 1.8V
ADC input analog signal could be power on/off during normal operation same as case #1.

There is no power sequence requiring, so they will decide case1 or case2 which better SNR than case3.
Is there any issue with these three different power supply case?
If case2 is possible (DVDD always on and AVDD on/off during operation), that is first priority.

>> I do not see any issue with AVDD/DVDD powered up and input signal is off. I also do not see any issue with only DVDD powered on and AVDD is turned on/off. Please remember device POR is referred to AVDD. So every time you will power off AVDD, device will reset.

Can you please elaborate more on what is AVDD_PMIC, AVDD_GNSS_3.3V. Do you have schematic capture that highlights ADC section.


2.Does it mean minimum 16 times SCK access required for calibration after power up?
>> For offset calibration after power up, CS should remain low for 16 clocks as shown in datasheet figure 36

3.At least 16 times SCK toggling required during CS=low for SPI access, is this mean first access required 16 times SCLK and CS=low after power up and calibration complete correctly?
CS glitch signal should be prevent during power up?
>> For offset calibration after power up, CS should remain low for 16 clocks as shown in datasheet figure 36. So any glitch on CS should be avoided during this time

4.How can customer know offset calibration is normal complete or abnormal case?
>> During normal operation CS should be kept low for 32 clock cycles to enter into offset calibration mode.
To verify offset calibration, you can short AINP to GND and then enter into normal calibration mode. The first conversion result will be off from 0V (device should show few tens of LSBs output code based on offset). This result is stored in device internal register. For subsequent conversions, the device adjusts the conversion results provided on the SDO output with the value stored in this internal register. Thus the second conversion result should be <10LSBs if input is shorted to GND as device will.

5.At least 32 times SCK access required during normal operation for recalibration?
>> Yes

6.If customer supply design AVDD=3.3V and DVDD=1.8V, there is power sequence between AVDD and DVDD.
DVDD 1.8V on first and AVDD 3.3V on after 5sec.
And only 3.3V AVDD 3.3V on/off during normal operation.
Is this possible supply design?
They will offset calibration access after AVDD on/off.
>> There is no supply sequencing required on AVDD and DVDD.

7.If AINN/P connected circuit power off while ADS7042 power on, AINM/P can detect voltage?
Is there any internal bias in ADS7042?
>> Device does not have any internal bias voltage.


Please let me know if you have any additional questions

Thanks & Regards
Abhijeet