Part Number: ADS52J90EVM
I am using TI's High speed ADC board ADS52J90EVM in JESD mode. I am using Xilinx Zynq Ultrascale+ board (zcu102) to read ADC samples using JESD204B interface.
I am able to see samples in ILA .
1- I am able to see the RAMP test patterns on ILA (as shown in figure
2- I am to get the custom test pattern on the ILA as well ( as shown in fig )
3- when i tried to see the external input signal ( sine wave, Ramp signal ). the output ( ADC_1 , i see in the ILA ) is a clipped off . ( as shown in figure ).
I have tried to change the amplitude and frequency of the external signal, but i receive the similar waveform ( for both sine and ramp signal) in FPGA.
Could you please help me out with this problem ?
