DAC37J82: 4-wire SPI mode

BobL

Part Number: DAC37J82
Other Parts Discussed in Thread: DAC38J84, DAC37J84

Support,

If I select 4-wire SPI mode with sif4_ena in register config2, does the SDIO pin tri-state during a read? I ask because I am trying to combine a bunch of 4-wire SPI devices to minimize I/O count and don't want to be driving the SDIs.

Thx,

Bobl

over 7 years ago

0 Jim Brinkhurst1 over 7 years ago

TI__Mastermind 44680 points

Hi Bob
We are looking into your question. Someone will provide a more detailed response shortly.
Best regards,
Jim B

0 jim s over 7 years ago in reply to Jim Brinkhurst1

TI__Guru* 91947 points

Bob,

Per the data sheet, both SDIO and SDO are active during the read cycle.

"Figure 59 shows the serial interface timing diagram for a DAC37J84/DAC38J84 read operation. SCLK is the

serial interface clock input to DAC37J84/DAC38J84. Serial data enable SDENB is an active low input to

DAC37J84/DAC38J84. SDIO is serial data in during the instruction cycle. In 3 terminal configuration, SDIO is

data out from the DAC37J84/DAC38J84 during the data transfer cycle, while SDO is in a high-impedance state.

In 4 terminal configuration, both SDIO and SDO are data out from the DAC37J84/DAC38J84 during the data

transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK

until the rising edge of SDENB when they will 3-state".

Regards,

Jim

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DAC37J82: 4-wire SPI mode