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ADC32RF45: ADC32RF80 Slow sp en setting?

HENRY JUNG
Expert 2030 points
Part Number: ADC32RF45
Other Parts Discussed in Thread: ADC32RF80, ADC32RF80EVM

Dears.

We are testing the ADC32RF80.

The test settings completed are as follows.

Sampling : 2949.12Mhz

Decimation : 6

BW : 300Mhz

LMFS : 4421

Sysref : 3.906Mhz

K=32.

I changed the sampling to 1.5Ghz and I can not link JESD204B.

There is a "SlOW SP EN" function in the data sheet.

Does the SLOW setting affect the JESD204B LINK?

Why can not I link when I lower the sampling to less than 2.5G?

 

Thank you.

  • 0
    TI__Mastermind 44680 points
    Hi Henry
    Are you using the ADC32RF80EVM and one of the TSW14JxxEVM capture boards or this with your own hardware?
    If you are using the TI evaluation boards, can you provide screen shots of the setup sequence you are using for the working and non-working configurations?
    If you are using your own hardware please provide the schematic details and register settings loaded to the ADC and any clocking devices.
    You can insert images into your post by clicking on the "Insert Code, Attach Files and more..." link below the right edge of the response box.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    TI__Expert 3515 points

    Henry,

    SLOW SP EN bits have to be set for sampling rates below 2.5Gsps. This could be the reason for the failed JESD link. This is stated in section 8.5.4.1 and 8.5.4.2

    Are you configuring the ADC with the ADC32RFxx EVM GUI? Then the GUI will program these bits once the lower sampling rate is chosen.

    Regards,

    satish.