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ADS1271: Clock Ratios of fSCLK and fCLK

user3874332
Prodigy 80 points
Part Number: ADS1271

Hello community,

I hope you all doing good :-).

In my current project I am using the ADS1271 High Speed Data Converter. I am just confused about the clock ratio of the SPI Clock (f_SCLK) and the Master Clock (f_CLK). On page 25 of the datasheet one can read in section "SCLK (SPI Format) that for best performance the ratio of f_SCLK and f_CLK should be limited to 1, 1/2, 1/4,.... 1/2^(n+1) for n=0,1,2,3.....  In my project I don't want to use a fixed sample rate so I want to make the master clock variable which leads with following equation fS=fCLK/512 to variable sample rates in SPI Mode. As micro controller I am using the STM32F429 which supports only fixed prescalers for the SPI. What happens if my ratio greater than 1, like 2,4,8... why I cannot achieve best performance if my SPI Clock is higher than my Master Clock ? After all, a higher SPI Clock would just read the bits faster out...

Thank you in advance !

best regards,

tuggy- bear :-)

  • 0
    TI__Guru 66256 points
    Hello,

    Thanks for your post!

    You will still meet the datasheet performance specs with any ratio of CLK and SCLK as long as you satisfy all of the SPI timing requirements. The recommendation for synchronizing their frequencies to some 2^n multiple of each other comes from empirical evaluation only, not from design. In general, clock signals (or intermodulation tones from the combination of clock signals) can couple into the analog output of the ADC and show up as added noise. If care is taken with regards to routing and handling of clock transients/reflections, I think using other SCLK frequencies in your system will be ok.

    Best Regards,