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Interfacing THS8200 with TVP5150

Mike Dielman
Prodigy 385 points
Other Parts Discussed in Thread: THS8200, TVP5150

We are using both the TVP5150 and THS8200 from TI to convert a compoiste NTSC signal to analog RGB. The video is converted however there is a purple hue on the RGB output, which indicates that the Green component is missing. When I put the THS8200 into the color bar test pattern I can see all of the colors so I know that there are no shorts on the board. I suspect that problem is with the TVP5150.  Can you provide me with some clues on what the problem is?

  • 0
    TI__Genius 16810 points

    Mike,

    Try the THS8200 settings below witch set up the CSC  YCbCr > RGB coefficients and CSM to scale to full-scale DAC outputs.  Horizontal timing and blank/sync amplitude settings for 480i60 are also included.  Let us know if this corrects your problem.

     Regards,

    Larry

     

    DATASET_NAME," 480i60Hz YCbCr to RGB Using SDTV CSC coefficients and CSM for Output Scaling "

    // Sync and blank level setup, SOG generated
    WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
    WR_REG,THS8200,0x01,0x1E,0x49 // dtg_y_sync2        
    WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
    WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
    WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
    WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
    WR_REG,THS8200,0x01,0x23,0x22 // dtg_y_sync_upper   
    WR_REG,THS8200,0x01,0x24,0x00 // dtg_cbcr_sync_upper

    //horizontal timing setup for 480i60 ouput
    WR_REG,THS8200,0x01,0x25,0x3E // dtg_spec_a         
    WR_REG,THS8200,0x01,0x26,0x14 // dtg_spec_b         
    WR_REG,THS8200,0x01,0x27,0x1E // dtg_spec_c         
    WR_REG,THS8200,0x01,0x28,0x79 // dtg_spec_d         
    WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1        
    WR_REG,THS8200,0x01,0x2A,0x00 // dtg_spec_e         
    WR_REG,THS8200,0x01,0x2B,0x01 // dtg_spec_h_msb     
    WR_REG,THS8200,0x01,0x2C,0x6B // dtg_spec_h_lsb     
    WR_REG,THS8200,0x01,0x2D,0x03 // dtg_spec_i_msb     
    WR_REG,THS8200,0x01,0x2E,0x1B // dtg_spec_i_lsb     
    WR_REG,THS8200,0x01,0x2F,0x11 // dtg_spec_k_lsb     
    WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb     
    WR_REG,THS8200,0x01,0x31,0x0A // dtg_spec_k1        
    WR_REG,THS8200,0x01,0x32,0xAD // dtg_speg_g_lsb     
    WR_REG,THS8200,0x01,0x33,0x01 // dtg_speg_g_msb     
    WR_REG,THS8200,0x01,0x34,0x03 // dtg_total_pixel_msb
    WR_REG,THS8200,0x01,0x35,0x5A // dtg_total_pixel_lsb
    WR_REG,THS8200,0x01,0x36,0x00 // dtg_linecnt_msb    
    WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    
    WR_REG,THS8200,0x01,0x38,0x84 // dtg_mode           
    WR_REG,THS8200,0x01,0x39,0x21 // dtg_frame_field_msb
    WR_REG,THS8200,0x01,0x3A,0x0D // dtg_frame_size_lsb 

                                     
    //CSC setup for YCbCr to RGB Conversion.  SDTV CSC coefficients used          
    WR_REG,THS8200,0x01,0x04,0x82 // csc_ric1           
    WR_REG,THS8200,0x01,0x05,0xCB // csc_rfc1           
    WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2           
    WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2           
    WR_REG,THS8200,0x01,0x08,0x05 // csc_ric3           
    WR_REG,THS8200,0x01,0x09,0x7B // csc_rfc3           
    WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1           
    WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1           
    WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2           
    WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2           
    WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3           
    WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3           
    WR_REG,THS8200,0x01,0x10,0x81 // csc_bic1           
    WR_REG,THS8200,0x01,0x11,0x58 // csc_bfc1           
    WR_REG,THS8200,0x01,0x12,0x06 // csc_bic2           
    WR_REG,THS8200,0x01,0x13,0xEF // csc_bfc2           
    WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3           
    WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3           
    WR_REG,THS8200,0x01,0x16,0x21 // csc_offset1        
    WR_REG,THS8200,0x01,0x17,0x2D // csc_offset12       
    WR_REG,THS8200,0x01,0x18,0xDA // csc_offset23       
    WR_REG,THS8200,0x01,0x19,0xBD // csc_offset3 

    //Map 64-940 RGB code range to 0-1023 full-scale range      
    WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
    WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
    WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
    WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
    WR_REG,THS8200,0x01,0x45,0x53 // csm_clip_bcb_high  
    WR_REG,THS8200,0x01,0x46,0x53 // csm_clip_rcr_high  
    WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
    WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
    WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
    WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb    
    WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
    WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb    
    WR_REG,THS8200,0x01,0x4D,0xAC // csm_mult_bcb_lsb   
    WR_REG,THS8200,0x01,0x4E,0xAC // csm_mult_rcr_lsb   
    WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode  

    WR_REG,THS8200,0x01,0x82,0x3B // Embedded syncs, RGB mode off