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ADS127L01: DRDY goes Low vs START pin is taken high in SPI mode

Ming Liao
Intellectual 450 points
Part Number: ADS127L01

Hi, 

In SPI mode, can START pin be taken low as soon as DRDY goes low? Or is there any timing delay necessary?

 

Thanks.

Ming

  • 0
    TI__Guru 51211 points
    Hi Ming,

    Thanks for your post!

    Please refer to section 8.4.3 of the ADS127L01 datasheet for information on the START pin in SPI mode.

    If START is pulled low, then DRDY will go high and the digital filter will reset requiring a delay for settling time before taking additional data. Once this settling is complete and data is ready for retrieval, DRDY will go back to low.

    If you pull START low as soon as DRDY goes low, the filter will continuously reset.

    Hope this helps!
  • 0 in reply to Alexander Smith
    Intellectual 450 points
    Hi Alex,

    In my new project, START pin is used to control the output data rate. Once DRDY goes low, MCU gets the interrupt to set CS at low for reading the new data, and can START pin be taken low at the same time as CS? Or should some tCLK need to be delay from DRDY going low to START taken high?

    There is no specific definition for the timing in the datasheet, or this is why I asked.

    Thanks for your help.

    Best Regards,
    Ming
  • 0 in reply to Ming Liao
    TI__Guru 51211 points

    Hi Ming,

    Pulling the START pin low will stop conversions and reset the digital filter. CS must remain low for the entire duration of the serial communication to complete data readback. Therefor, START should be held high for the duration of the data readback, then can be taken low. The length of this duration will depend on your SCLK speed and mode for data retrieval.

  • 0 in reply to Alexander Smith
    TI__Guru 63196 points
    Hi Ming,

    Just to be clear, why is it that you want to toggle the START pin at all? During data collection, the START pin should remain high. The ADC will convert and output data continuously. Each time /DRDY goes low, the output shift register has been updated with new data. Like Alex said, /CS will be brought low and must remain low throughout the duration of the data readback.

    While you are reading the data after /DRDY goes low, the ADC is already converting the next sample. You cannot interrupt the conversion process without resetting the digital filter and introducing significant delays between samples.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Intellectual 450 points

    Hi Ryan,

    The design requirements are as follows:
    1. The input signal bandwidth: 10KHz
    2. The output data rate: adjustable from 20KSPS to 40KSPS
    3. One SPI interface are shared with Four ADS127L01 devices
    4. ADC fCLK = SPI SCLK = 16.384MHz

    Therefore, Low-latency filter with OSR 128 will be selected, and the minimum period from START low, START high, DRDY low, CS low to CS high is 4 tCLK + 10ns + 5 tCLK + 288 tCLK + 96 (24*4) tCLK ~= 24us, so to toggle START pin, the maximum output data rate can be around 41.6KSPS, right?

    Best Regards,
    Ming

  • 0 in reply to Ming Liao
    TI__Guru 63196 points

    Hello Ming,

    I understand that you are trying to adjust the output data rate, but toggling the START pin is not the correct way to do it with this device. Delta-sigma ADCs are intended to convert continuously. The digital filter relies on a history of previous samples to compute a low-noise average signal at the output.

    The START pin must remain high in order to collect samples at a fixed periodic rate. To adjust the data rate, it is best to adjust the master CLK frequency and the OSR. For example, CLK = 4.096 MHz and OSR = 128 will produce an output data rate of 32 kSPS. This gives you a -3 dB signal bandwidth of about 12.65 kHz. You will have 31.25 us between /DRDY falling edges to enable the SPI interface (/CS = low), read the data (4 * 8 bits * n devices), and disable the interface (/CS = high). You do not have to return /CS high - it can remain low during the entire collection routine. Each time /DRDY pulses low, you simply need to send more SCLKs to the ADC and clock out the data.

    Please refer to the ADS127L01 Excel Calculator Tool at the link below. The "Multiple Device Configuration" tab calculates how many devices can be configured in a daisy-chain or cascaded configuration.

    Best Regards,