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How to reduce ADC clock jitter?

Vaishali Sridhar
Prodigy 80 points
Part Number: ADS42LB69


I am using ADS42LB69 ADC. After data acquisition and plotting in ADC analyzer, I observe that the noise floor is shifted(i.e, if ideal noise floor is at -113, @ 10dBm noise floor is at -103)  for higher power level and as i acquire data at lower power levels, the noise shifts down to ideal value. This noise floor shift is due to clock jitter and this affects the SNR achievable me. Can someone help me as to how to achieve stable noise floor?

  • 0
    TI__Mastermind 44680 points

    Hi Vaishali

    Optimum SNR and noise floor are achieved by using a low jitter clock source as discussed in section 9.2.2.3 of the ADS42LB69 datasheet.

    What are you using as the clock source for the ADS42LB69?

    Can you share the schematic for your ADC and related circuitry?

    What is the frequency of the input signal?

    Best regards,

    Jim B