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ADS42LB69: what is the solution to improve ENOB and SNR of ADS42LB69

Vaishali Sridhar
Prodigy 80 points
Part Number: ADS42LB69

I am using ADS42LB69 ADC in my design. I am trying to achieve the best possilble SNR provided in the datasheet(>70 dBFS). During testing, initially noise floor data was acquired and the ENOB for noise floor achieved is 10.5bits(manual calculation) and while plotting in ADC analyzer tool ENOB achieved is 12 bits. The former ENOB is a static ENOB. The dynamic ENOB provided in the datasheet is 11.8. But I am able to achieve only 10.4bits. As per calculation only 4 bits to be missed to achieve static ENOB of 12 and hence the noise floor count difference should be around 20 counts. But in my design I am getting the count variation as 40.

The following debugging methods have been adopted to reduce the noise floor count variation,

  1. The PSRR of ADC has been checked, as per datasheet PSRR is >40 dB and my power supply filter is designed in such a way that only 15mV is seen at ADC input which falls within the spec.

  2. External clock has been provided and tested with using narrow bandwidth filters.

  3. I have tested for ADC performance with datasheet recommended front end as well as my own altered front end which you can find below,

Still I could not find any improvement in ENOB.

Please help me out to improve the ADC performance.

  • 0
    TI__Guru* 91947 points

    Vaishali,

    What sample rate is the ADC running at? What IF are you sending the ADC? Is the IF filtered? What amplitude is this input at? Please send the ADC register configuration you are using and I will see what we can do to help you.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 80 points

    My previous question on how to reduce clock jitter is also related to ENOB and SNR  issue.

    Analog input - 180MHz

    Sampling rate - 240MHz.

    Yes I am using a Band pass filter for both IF and clock input.

    1) I am using the ADC for wide band width from 140MHz to 220MHz. So for IF i am using a wide bandwidth  filter. For clock i used narrow band filter.

    2) I am attaching the clock and analog input front end circuit.

    ads42lb69 clock and analog front end.pdf

    3) I am using the following registers to configure my ADC and the sequence is as provided  below,

    Addr    Data
    0x8    0xC
    0x15    0x1
    0xF    0x66
    0x10    0xA1
    0x11    0x9C

    Once the pattern is locked, I will be providing the IF and following the configuration sequence as shown below,

    Addr,Data
    0x8,0xC
    0x15,0x1
    0xF,0x0

    4) The balun  used in IF front is TC1-1-13M+ and i tried changing it to TC1-1 and tested but still no performance improvement.

    Please help me with this issue and also where to check if the common mode voltage is proper in my circuit.

  • 0 in reply to Vaishali Sridhar
    TI__Guru* 91947 points

    Vaishali,

    I followed the instructions attached and loaded the config file that is all attached and got a good performing output using your clock and IF setup values. Compare these register settings to what you have.

    Regards,

    Jim

    TSW1400_Normal_LVDS_Swing.cfgADS42LB69_Fs_240M_IF_180.1M.pptx

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Vaishali,

    This is good news. Since you are not requesting anything else, I am going to close this ticket.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 80 points
    Hi Jim,

    I will test the ADC with the registers that you have provided and look into the performance.
    Can you tell what type of filter you have used for clock and analog signal?

    Regards,
    Vaishali Sridhar
  • 0 in reply to Vaishali Sridhar
    TI__Guru* 91947 points

    Vaishali,

    They were bandpass filters from TTE.

    Regards,

    Jim