DAC37J84: DAC37J84

serkan unal

Part Number: DAC37J84
Other Parts Discussed in Thread: LMK04828,

hi,

we are using LMK04828 and DAC37J84. We are facing a problem at SYNC signal of DAC. It always stays at HIGH but as i know from JESD204 it should assert LOW at the begginning of link establishment. In normal process it should assert LOW and JESD204 core should send ILAS and after link establishment DAC should assert sync signal HIGH. We checked our sysref is present at the beginning. We also tried periodic sysref but sync do not goes to LOW at any point.

Do you have any comment?

over 8 years ago

0 Ebenezer Dwobeng over 8 years ago

TI__Genius 9695 points

Hi Serkan,

The SYNC should be pulled low after completing step 13 of the DAC startup sequence, when the init registers are cleared. Please refer to section 8.3 of datasheet.

Thanks,
Eben.

0 TAYLAN ERTAŞ over 8 years ago in reply to Ebenezer Dwobeng

Prodigy 100 points

Hi Ebenezer,

Here are the details of our observations & configuration

The configuration:

a. (Quad channel) LMFS: 4421, HD=0, No interpolation (1X), No scramble, K=16

b. DACCLK = 400 MHz (F_dac = 400 Msps) => F_line = 8 Gbps.

c. F_LMFC = F_line/10/F/K=25 MHz, F_SYSREF=F_LMFC/n-integer=3.125 MHz for n-integer = 5

d. Lanes (0 to 3) are used. Link-0 is configured for JESD.

e. 8-SYSREF pulses are generated instead of continuous SYSREF.

Note: We use our custom hardware (consists of Zynq XC7Z045-2FFG676, DAC37J84, LMK4828), not EVMs. All clocks are generated successfully.

You can find LMK4828 and DAC37J84 configuration registers and functions in the attached files.

The functions "hal_lmk_init()" and "hal_dac_init()" is for LMK and DAC configuration, respectively, and we try to apply the procedure in the section "7.5 Typical Start-up Procedure for AC Coupled SYSREF Network" of the document "SLAA656: DAC3xJ8x Device Initialization and SYSREF Configuration". This procedure is smilar to the one in the section "8.3 Initialization Set-up" of DAC datasheet.

Observations:

a. Step-5: After setting all registers, SERDES PLLs are locked
b. Step-6: it is observed that SYNCB is in HIGH logic after programming config74 (0x4A) to initialize JESD204B block of the DAC (that is, init_state = 4b’1111 and jesd_reset_n = 1b’0).

c. Step-7: "alarm_sysref_err" of Reg-0x6C is all zero, inactive. i ignore sysref alarm register for now because i already programmed registers 0x24 & 0x5c at this point and also SYSREF pulses are not generated yet. But i will investigate it later.
d. Step-14: After generating SYSREF pulses (step-14), it is observed that SYNCB signal still is kept in HIGH logic at the scope. i also check SYNC_N_AB signal and it has the same behaviour.
e. Step-16: alarm registers as follows:

      i. Reg-0x6C              : 0x0003 (DAC PLL Out of lock since it is not used)
      ii. Reg-0x64 to 0x6B : 0x0001 (Read FIFO Empty for all lanes)
      iii.Reg-0x6D               : 0x0000 (No alarm)

Same problem occurs in different hardwares. It seems that JESD module of DAC is not working properly.

By the way, i couldn't find any info about JESDCLK divider (Reg-0x25[15:13]) in the document. So i set it to DIV-16 referring to TI DAC37j84EVM application/program. F_JESDCLK becomes 400 / 16 = 25 MHz. Could you give more detailed info about this, please?

Best Regards,

Taylan

Fullscreen hal_lmk.c Download

// ===========================================================================
// Include Files
// ---------------------------------------------------------------------------
#include "hal_dbg.h"
#include "hal_lmk.h"
#include "hal_spi.h"
#include "hal_timer.h"

// ===========================================================================
// External Data Definitions
// ---------------------------------------------------------------------------

// ===========================================================================
// Local Defines
// ---------------------------------------------------------------------------
#define LMK_DEFAULT_REGS_LENGTH						113

#define LMK_LOCK_TIMEOUT_US							3000
#define LMK_LOCK_TIMEOUT_MS							1000
//#define LMK_LOCK_TIMEOUT							(LMK_LOCK_TIMEOUT_US * HAL_TIMER_USEC_PRESCALAR)
#define LMK_LOCK_TIMEOUT							(LMK_LOCK_TIMEOUT_MS * HAL_TIMER_MSEC_PRESCALAR)

// ===========================================================================
// Local Structures
// ---------------------------------------------------------------------------

// ===========================================================================
// Local Data Definitions
// ---------------------------------------------------------------------------
SPI_HANDLE_Type	*lmk_spi_handle;


// Osc = 80 MHz & DAC
const u16 lmk_modem_default_cfg_regs[LMK_DEFAULT_REGS_LENGTH][2] = {
	{0x0000, 	0x90},		// RESET[b7]=1-Reset, SPI_3WIRE_DIS[b4]=1-4Wire
	{0x0000, 	0x10},		// RESET[b7]=0-Normal, SPI_3WIRE_DIS[b4]=1-4Wire
	{0x0002, 	0x00},		// POWER_DOWN[b0]=0-Disabled

	{0x0100, 	0x18}, 		// Clkout0_1_ODL[b6] = 0, Clkout0_1_IDL[b5] = 0, DCLKout0_DIV[b4:b0] = 24 (MGT_REFCLK0: 100 MHz / MGT_RX_SYSREF)
	{0x0101, 	0x55},		// DCLKout0_DDLY_CNTH[b7:b4] = 5, DCLKout0_DDLY_CNTL[b3:b0] = 5
	{0x0103, 	0x01},		// DCLKout0_ADLY[b7:b3] = 0 ps, DCLKout0_ADLY_MUX[b2] = 0, DCLKout0_MUX[b1:b0] = 1-Divider with DutyCycleCorr and HalfStep
	{0x0104, 	0x20},		// DCLKout0_HS[b6] = 0 cycle, SDCLKout1_MUX[b5] = 1-SYSREF, SDCLKout1_DDLY[b4:b1] = 0-Bypass, SDCLKout1_HS[b0] = 0 cycle
	{0x0105, 	0x00},		// SDCLKout1_ADLY_EN[b4] = 0-Disabled, SDCLKout1_ADLY[b3:b0] = 0 ps
	{0x0106, 	0xF0},		// DCLKout0_DDLY_PD[b7] = 1-PwrDwn, DCLKout0_HSg_PD[b6] = 1-PwrDwn, DCLKout0_ADLYg_PD[b5] = 1-PwrDwn, DCLKout0_ADLY_PD[b4] = 1-PwrDwn, CLKout0_1_PD[b3] = 0-Enabled, SDCLKout1_DIS_MODE[b2:b1] = 0-Active, SDCLKout1_PD[b0] = 0-Enabled
	{0x0107, 	0x55},		// SDCLKout1_POL[b7] = 0-Normal, SDCLKout1_FMT[b6:b4] = 5-LVPECL1600, DCLKout0_POL[b3] = 0-Normal, DCLKout0_FMT[b2:b0] = 5-LVPECL1600

	{0x0108, 	0x0C},		// Clkout2_3_ODL[b6] = 0, Clkout2_3_IDL[b5] = 0, DCLKout2_DIV[b4:b0] = 12 (JESD204B_TX_CORECLK/JESD204B_RX_CORECLK: 200 MHz)
	{0x0109, 	0x55},		// DCLKout2_DDLY_CNTH[b7:b4] = 5, DCLKout2_DDLY_CNTL[b3:b0] = 5
	{0x010B, 	0x01},		// DCLKout2_ADLY[b7:b3] = 0 ps, DCLKout2_ADLY_MUX[b2] = 0, DCLKout2_MUX[b1:b0] = 1-Divider with DutyCycleCorr and HalfStep
	{0x010C, 	0x20},		// DCLKout2_HS[b6] = 0 cycle, SDCLKout3_MUX[b5] = 1-SYSREF, SDCLKout3_DDLY[b4:b1] = 0-Bypass, SDCLKout3_HS[b0] = 0 cycle
	{0x010D, 	0x00},		// SDCLKout3_ADLY_EN[b4] = 0-Disabled, SDCLKout3_ADLY[b3:b0] = 0 ps
	{0x010E, 	0xF0},		// DCLKout2_DDLY_PD[b7] = 1-PwrDwn, DCLKout2_HSg_PD[b6] = 1-PwrDwn, DCLKout2_ADLYg_PD[b5] = 1-PwrDwn, DCLKout2_ADLY_PD[b4] = 1-PwrDwn, CLKout2_3_PD[b3] = 0-Enabled, SDCLKout3_DIS_MODE[b2:b1] = 0-Active, SDCLKout3_PD[b0] = 0-Enabled
	{0x010F, 	0x55},		// SDCLKout3_POL[b7] = 0-Normal, SDCLKout3_FMT[b6:b4] = 5-LVPECL1600, DCLKout2_POL[b3] = 0-Normal, DCLKout2_FMT[b2:b0] = 5-LVPECL1600

	{0x0110, 	0x18}, 		// Clkout4_5_ODL[b6] = 0, Clkout4_5_IDL[b5] = 0, DCLKout4_DIV[b4:b0] = 24 (MGT_REFCLK2_DAC: 100 MHz / MGT_TX_SYSREF)
	{0x0111, 	0x55},		// DCLKout4_DDLY_CNTH[b7:b4] = 5, DCLKout4_DDLY_CNTL[b3:b0] = 5
	{0x0113, 	0x01},		// DCLKout4_ADLY[b7:b3] = 0 ps, DCLKout4_ADLY_MUX[b2] = 0, DCLKout4_MUX[b1:b0] = 1-Divider with DutyCycleCorr and HalfStep
	{0x0114, 	0x20},		// DCLKout4_HS[b6] = 0 cycle, SDCLKout5_MUX[b5] = 1-SYSREF, SDCLKout5_DDLY[b4:b1] = 0-Bypass, SDCLKout5_HS[b0] = 0 cycle
	{0x0115, 	0x00},		// SDCLKout5_ADLY_EN[b4] = 0-Disabled, SDCLKout5_ADLY[b3:b0] = 0 ps
	{0x0116, 	0xF0},		// DCLKout4_DDLY_PD[b7] = 1-PwrDwn, DCLKout4_HSg_PD[b6] = 1-PwrDwn, DCLKout4_ADLYg_PD[b5] = 1-PwrDwn, DCLKout4_ADLY_PD[b4] = 1-PwrDwn, CLKout4_5_PD[b3] = 0-Enabled, SDCLKout5_DIS_MODE[b2:b1] = 0-Active, SDCLKout5_PD[b0] = 0-Enabled
{0x0117, 	0x15},//0x11},		// SDCLKout5_POL[b7] = 0-Normal, SDCLKout5_FMT[b6:b4] = 1-LVDS, DCLKout4_POL[b3] = 0-Normal, DCLKout4_FMT[b2:b0] = 1-LVDS

	{0x0118, 	0x06},		// Clkout6_7_ODL[b6] = 0, Clkout6_7_IDL[b5] = 0, DCLKout6_DIV[b4:b0] = 6 (DAC_TX_CLKIN: 400 MHz / DAC_TX_SYSREF)
	{0x0119, 	0x55},		// DCLKout6_DDLY_CNTH[b7:b4] = 5, DCLKout6_DDLY_CNTL[b3:b0] = 5
	{0x011B, 	0x01},		// DCLKout6_ADLY[b7:b3] = 0 ps, DCLKout6_ADLY_MUX[b2] = 0, DCLKout6_MUX[b1:b0] = 1-Divider with DutyCycleCorr and HalfStep
	{0x011C, 	0x20},		// DCLKout6_HS[b6] = 0 cycle, SDCLKout7_MUX[b5] = 1-SYSREF, SDCLKout7_DDLY[b4:b1] = 0-Bypass, SDCLKout7_HS[b0] = 0 cycle
	{0x011D, 	0x00},		// SDCLKout7_ADLY_EN[b4] = 0-Disabled, SDCLKout7_ADLY[b3:b0] = 0 ps
	{0x011E, 	0xF0},		// DCLKout6_DDLY_PD[b7] = 1-PwrDwn, DCLKout6_HSg_PD[b6] = 1-PwrDwn, DCLKout6_ADLYg_PD[b5] = 1-PwrDwn, DCLKout6_ADLY_PD[b4] = 1-PwrDwn, CLKout6_7_PD[b3] = 0-Enabled, SDCLKout7_DIS_MODE[b2:b1] = 0-Active, SDCLKout7_PD[b0] = 0-Enabled
	{0x011F, 	0x55},		// SDCLKout7_POL[b7] = 0-Normal, SDCLKout7_FMT[b6:b4] = 5-LVPECL1600, DCLKout6_POL[b3] = 0-Normal, DCLKout6_FMT[b2:b0] = 5-LVPECL1600

	{0x0120, 	0x0C}, 		// Clkout8_9_ODL[b6] = 0, Clkout8_9_IDL[b5] = 0, DCLKout8_DIV[b4:b0] = 12 (FPGA_CLK: 200 MHz)
	{0x0121, 	0x55},		// DCLKout8_DDLY_CNTH[b7:b4] = 5, DCLKout8_DDLY_CNTL[b3:b0] = 5
	{0x0123, 	0x01},		// DCLKout8_ADLY[b7:b3] = 0 ps, DCLKout8_ADLY_MUX[b2] = 0, DCLKout8_MUX[b1:b0] = 1-Divider with DutyCycleCorr and HalfStep
	{0x0124, 	0x20},		// DCLKout8_HS[b6] = 0 cycle, SDCLKout9_MUX[b5] = 1-SYSREF, SDCLKout9_DDLY[b4:b1] = 0-Bypass, SDCLKout9_HS[b0] = 0 cycle
	{0x0125, 	0x00},		// SDCLKout9_ADLY_EN[b4] = 0-Disabled, SDCLKout9_ADLY[b3:b0] = 0 ps
	{0x0126, 	0xF1},		// DCLKout8_DDLY_PD[b7] = 1-PwrDwn, DCLKout8_HSg_PD[b6] = 1-PwrDwn, DCLKout8_ADLYg_PD[b5] = 1-PwrDwn, DCLKout8_ADLY_PD[b4] = 1-PwrDwn, CLKout8_9_PD[b3] = 0-Enabled, SDCLKout9_DIS_MODE[b2:b1] = 0-Active, SDCLKout9_PD[b0] = 1-PwrDwn
{0x0127, 	0x05},//0x01},		// SDCLKout9_POL[b7] = 0-Normal, SDCLKout9_FMT[b6:b4] = 0-PwrDwn, DCLKout8_POL[b3] = 0-Normal, DCLKout8_FMT[b2:b0] = 1-LVDS

	{0x0128, 	0x00},		// Clkout10_11_ODL[b6] = 0, Clkout10_11_IDL[b5] = 0, DCLKout10_DIV[b4:b0] = 32
	{0x0129, 	0x55},		// DCLKout10_DDLY_CNTH[b7:b4] = 5, DCLKout0_DDLY_CNTL[b3:b0] = 5
	{0x012B, 	0x01},		// DCLKout10_ADLY[b7:b3] = 0 ps, DCLKout10_ADLY_MUX[b2] = 0, DCLKout10_MUX[b1:b0] = 1-Divider with DutyCycleCorr and HalfStep
	{0x012C, 	0x20},		// DCLKout10_HS[b6] = 0 cycle, SDCLKout11_MUX[b5] = 1-SYSREF, SDCLKout11_DDLY[b4:b1] = 0-Bypass, SDCLKout11_HS[b0] = 0 cycle
	{0x012D, 	0x00},		// SDCLKout11_ADLY_EN[b4] = 0-Disabled, SDCLKout11_ADLY[b3:b0] = 0 ps
	{0x012E, 	0xF9},		// DCLKout10_DDLY_PD[b7] = 1-PwrDwn, DCLKout10_HSg_PD[b6] = 1-PwrDwn, DCLKout10_ADLYg_PD[b5] = 1-PwrDwn, DCLKout10_ADLY_PD[b4] = 1-PwrDwn, CLKout10_11_PD[b3] = 1-PwrDwn, SDCLKout11_DIS_MODE[b2:b1] = 0-Active, SDCLKout11_PD[b0] = 1-PwrDwn
	{0x012F, 	0x00},		// SDCLKout11_POL[b7] = 0-Normal, SDCLKout11_FMT[b6:b4] = 0-PwrDwn, DCLKout10_POL[b3] = 0-Normal, DCLKout10_FMT[b2:b0] = 0-PwrDwn

	{0x0130, 	0x03}, 		// Clkout12_13_ODL[b6] = 0, Clkout12_13_IDL[b5] = 0, DCLKout12_DIV[b4:b0] = 3 (ADC_IF_CLKIN: 800 MHz / ADC_IF_SYSREF)
	{0x0131, 	0x55},		// DCLKout12_DDLY_CNTH[b7:b4] = 5, DCLKout12_DDLY_CNTL[b3:b0] = 5
	{0x0133, 	0x01},		// DCLKout12_ADLY[b7:b3] = 0 ps, DCLKout12_ADLY_MUX[b2] = 0, DCLKout12_MUX[b1:b0] = 1-Divider with DutyCycleCorr and HalfStep
	{0x0134, 	0x20},		// DCLKout12_HS[b6] = 0 cycle, SDCLKout13_MUX[b5] = 1-SYSREF, SDCLKout13_DDLY[b4:b1] = 0-Bypass, SDCLKout13_HS[b0] = 0 cycle
	{0x0135, 	0x00},		// SDCLKout13_ADLY_EN[b4] = 0-Disabled, SDCLKout13_ADLY[b3:b0] = 0 ps
	{0x0136, 	0xF0},		// DCLKout12_DDLY_PD[b7] = 1-PwrDwn, DCLKout12_HSg_PD[b6] = 1-PwrDwn, DCLKout12_ADLYg_PD[b5] = 1-PwrDwn, DCLKout12_ADLY_PD[b4] = 1-PwrDwn, CLKout12_13_PD[b3] = 0-Enabled, SDCLKout13_DIS_MODE[b2:b1] = 0-Active, SDCLKout13_PD[b0] = 0-Enabled
	{0x0137, 	0x55},		// SDCLKout13_POL[b7] = 0-Normal, SDCLKout13_FMT[b6:b4] = 5-LVPECL1600, DCLKout12_POL[b3] = 0-Normal, DCLKout12_FMT[b2:b0] = 5-LVPECL1600

	{0x0138, 	0x04},		// VCO_MUX[b6:b5] = 0-VCO0, OSCout_MUX[b4] = 0-Buffered OSCin, OSCout_FMT[b3:b0] = 4-LVPECL1600
{0x0139, 	0x02},//0x00},		// SYSREF_CLKin_MUX[b2] = 0-SYSREF Mux, SYSREF_Mux[b1:b0] = 0-NormalSync
	{0x013A, 	0x03}, 		// SYSREF_DIV_12_8[b4:b0] = Div-768 (F_LMFC_DAC=F_line/10/F/K=25 MHz, F_SYSREF=F_LMFC_DAC/n-integer=3.125 MHz for n-integer=8)
	{0x013B, 	0x00},		// SYSREF_DIV_7_0[b7:b0] = Div-768 (F_LMFC_ADC=F_line/10/F/K=50 MHz, F_SYSREF=F_LMFC_ADC/2^n-integer=3.125 MHz for n-integer=4)
	{0x013C, 	0x00},		// SYSREF_DDLY_12_8[b4:b0] = DDLY-8
	{0x013D, 	0x08},		// SYSREF_DDLY_7_0[b7:b0] = DDLY-8
	{0x013E, 	0x03},		// SYSREF_PULSE_CNT[b1:b0] = 3 - 8 pulses
	{0x013F, 	0x0B},		// PLL2_NCLK_MUX[b4] = 0-PLL2 Prescalar, PLL1_NCLK_MUX[b3] = 1-FeedbackMux, FB_MUX[b2:b1] = 1-DCLKout8(FPGA_CLK), FB_MUX_EN[b0] = 1-Enabled
	{0x0140, 	0x00},		// PLL1_PD[b7]=0-Normal, VCO_LDO_PD[b6]=0-Normal, VCO_PD[b5]=0-Normal, OSCin_PD[b4]=0-Normal, SYSREF_GLB_PD[b3]=0-Normal, SYSREF_PD[b2]=0-Normal, SYSREF_DDLY_PD[b1]=0-Normal, SYSREF_PLSR_PD[b7]=0-Normal
	{0x0141, 	0x00},		// DDLYd_SYSREF_EN[b7]=0-Disabled, DDLYd_12_EN[b6]=0-Disabled, DDLYd_10_EN[b5]=0-Disabled, DDLYd_8_EN[b4]=0-Disabled, DDLYd_6_EN[b3]=0-Disabled, DDLYd_4_EN[b2]=0-Disabled, DDLYd_2_EN[b1]=0-Disabled, DDLYd_0_EN[b0]=0-Disabled,
	{0x0142, 	0x00},		// DDLYd_STEP_CNT[b3:b0] = 0-No Adjust
{0x0143, 	0x92},//0x91},		// SYSREF_CLR[b7]=1, SYNC_1SHOT_EN[b6]=0-Disabled, SYNC_POL[b5]=0-Normal, SYNC_EN[b4]=1-Enabled, SYNC_PLL2_DLD[b3]=0-OFF, SYNC_PLL1_DLD[b2]=0-OFF, SYNC_MODE[b1:b0]=1-"SYNC event generated from SYNC pin"
	{0x0144, 	0xFF},		// SYNC_DISSYSREF[b7]=1-"Prevent the SYSREF clocks from becoming synchronized during a SYNC event", SYNC_12_DIS[b6]=1-SyncDisabled, SYNC_10_DIS[b5]=1-SyncDisabled, SYNC_8_DIS[b4]=1-SyncDisabled, SYNC_6_DIS[b3]=1-SyncDisabled, SYNC_4_DIS[b2]=1-SyncDisabled, SYNC_2_DIS[b1]=1-SyncDisabled, SYNC_0_DIS[b0]=1-SyncDisabled
	{0x0145, 	0x7F},		// Always 0x7F
	{0x0146, 	0x18},		// CLKin2_EN[b5]=0-DisableAutoMode, CLKin1_EN[b4]=1-EnableAutoMode, CLKin0_EN[b3]=1-EnableAutoMode, CLKin2_TYPE[b2]=0-Bipolar, CLKin1_TYPE[b1]=0-Bipolar, CLKin0_TYPE[b0]=0-Bipolar
	{0x0147, 	0x3A},		// CLKin_SEL_POL[b7]=0-ActiveHigh, CLKin_SEL_MODE[b6:b4]=3-PinSelect, CLKin1_OUT_MUX[b3:b2]=2-PLL1, CLKin0_OUT_MUX[b1:b0]=2-PLL1
	{0x0148, 	0x02},		// CLKin_SEL0_MUX[b5:b3]=0-LogicLow, CLKin_SEL0_TYPE[b2:b0]=2-Input/w pull-dwn
	{0x0149, 	0x73},		// SDIO_RDBK_TYPE[b6]=1-Output OpenDrain in 3-wire mode, CLKin_SEL1_MUX[b5:b3]=6-SPI Readback, CLKin_SEL1_TYPE[b2:b0]=3-Output pushpull
	{0x014A, 	0x02},		// RESET_MUX[b5:b3]=0-LogicLow, RESET_TYPE[b2:b0]=2-Input/w pull-dwn
	{0x014B, 	0x16},		// LOS_TIMEOUT[b7:b6]=0-370 kHz, LOS_EN[b5]=0-Disabled, TRACK_EN[b4]=1-Enabled, HOLDOVER_FORCE[b3]=0-Disabled, MAN_DAC_EN[b2]=1-Manual, MAN_DAC[b1:b0]= 512
	{0x014C, 	0x00},		// MAN_DAC[b7:b0] = 512
	{0x014D, 	0x00},		// DAC_TRIP_LOW[b5:b0]=0- 1/Vcc*64
	{0x014E, 	0xC0},		// DAC_CLK_MULT[b7:b6]=3-16384, DAC_TRIP_HIGH[b5:b0]=0-1/Vcc*64
	{0x014F, 	0x7F},		// DAC_CLK_CNTR[b7:b0]=127
	{0x0150, 	0x00},		// CLKin_OVERRIDE[b6]=0-No override, HOLDOVER_PLL1_DET[b4]=0, HOLDOVER_LOS_DET[b3]=0-Disabled, HOLDOVER_VTUNE_SET[b2]=0-Disabled, HOLDOVER_HITLESS_SWITCH[b1]=0-HardSwitch, HOLDOVER_EN[b0]=0-Disabled

	{0x0151, 	0x02},		// HOLDOVER_DLD_CNTR[b5:b0]=512
	{0x0152, 	0x00},		// HOLDOVER_DLD_CNTR[b7:b0]=512
	{0x0153, 	0x00},		// CLKin0_R[b5:b0]=80 (CLKin = 80 MHz, PLL1_Fpd = 1 MHz, max:40 MHz)
	{0x0154, 	0x50},		// CLKin0_R[b7:b0]=80
	{0x0155, 	0x00},		// CLKin1_R[b5:b0]=80 (CLKin = 80 MHz, PLL1_Fpd = 1 MHz, max:40 MHz)
	{0x0156, 	0x50},		// CLKin1_R[b7:b0]=80
	{0x0157, 	0x00},		// CLKin2_R[b5:b0]=80 (CLKin = 80 MHz, PLL1_Fpd = 1 MHz, max:40 MHz)
	{0x0158, 	0x50},		// CLKin2_R[b7:b0]=80
	{0x0159, 	0x00},		// PLL1_N[b5:b0]=200 (FB-FPGA_CLK=200 MHz)
	{0x015A, 	0xC8},		// PLL1_N[b7:b0]=200 (FB-FPGA_CLK=200 MHz)
	{0x015B, 	0xDF},		// PLL1_WND_SIZE[b7:b6]=3-43ns, PLL1_CP_TRI[b5]=0-PLL1 CPout active, PLL1_CP_POL[b4]=1-PositiveSLope, PLL1_CP_GAIN[b3:b0]=15-1550uA
	{0x015C, 	0x20},		// PLL1_DLD_CNT[b5:b0]= 8192
	{0x015D, 	0x00},		// PLL1_DLD_CNT[b7:b0]= 8192
	{0x015E, 	0x00},		// PLL1_R_DLY[b5:b3]=0-0ps, PLL1_N_DLY[b2:b0]=0-0ps
	{0x015F, 	0x0B},		// PLL1_LD_MUX[b7:b3]=1-PLL1 DLD, PLL1_LD_TYPE[b2:b0]=3-Output pushpull
	{0x0160, 	0x00},		// PLL2_R[b3:b0]=1 (OScin = 80 MHz, PLL2_Fpd = 80 MHz, max:155 MHz)
	{0x0161, 	0x01},		// PLL2_R[b7:b0]=1 (OScin = 80 MHz, PLL2_Fpd = 80 MHz, max:155 MHz)
	{0x0162, 	0x24},		// PLL2_P[b7:b5]=1-NPre=2, OSCin_FREQ[b4:b2]=1-67/127 MHz, PLL2_XTAL_EN[b1]=0-OSCAmp Disabled, PLL2_REF_2X_EN[b0]=0-Disabled
	{0x0163, 	0x00},		// PLL2_N_CAL[b1:b0]=12
	{0x0164, 	0x00},		// PLL2_N_CAL[b7:b0]=12
	{0x0165, 	0x0C},		// PLL2_N_CAL[b7:b0]=12

	//{0x0171, 	0xAA},		//
	//{0x0172, 	0x02},		//
	{0x017C, 	0x15},		// OPT_REG_1[b7:b0]=21-LMK04828
	{0x017D, 	0x33},		// OPT_REG_2[b7:b0]=51-LMK04828

	{0x0166, 	0x00},		// PLL2_FCAL_DIS[b2]=0-FCal Enabled, PLL2_N[b1:b0]=15 (PLL2_Fpd=80 MHz, max:155 MHz)
	{0x0167, 	0x00},		// PLL2_N[b7:b0]=15
	{0x0168, 	0x0F},		// PLL2_N[b7:b0]=15
	{0x0169, 	0x59},		// PLL2_WND_SIZE[b6:b5]=2-3.7ns, PLL2_CP_GAIN[b4:b3]=3-3.2 mA, PLL2_CP_POL[b2]=0-NegativeSlope, PLL2_CP_TRI[b1]=0-Disabled
	{0x016A, 	0x20},		// SYSREF_REQ_EN[b6]=0-Disabled, PLL2_DLD_CNT[b5:b0]=8192
	{0x016B, 	0x00},		// PLL2_DLD_CNT[b5:b0]=8192
	{0x016C, 	0x00},		// PLL2_LF_R4[b5:b3]=0-200 Ohm, PLL2_RF_R3[b2:b0]=0-200 Ohm
	{0x016D, 	0x00},		// PLL2_LF_C4[b7:b4]=0-10 pF, PLL2_RF_C3[b3:b0]=0-10 pF
	{0x016E, 	0x13},		// PLL2_LD_MUX[b7:b3]= 2-PLL2 DLD, PLL2_LD_TYPE[b2:b0]=3-Output pushpull
	//{0x0171, 	0xAA},
	//{0x0172, 	0x02},
	{0x0173, 	0x00},		// PLL2_PRE_PD[b6]=0-Normal, PLL2_PD[b5]=0-Normal
	//{0x017C, 	0x15},		// OPT_REG_1[b7:b0]=21-LMK04828
	//{0x017D, 	0x33},		// OPT_REG_2[b7:b0]=51-LMK04828
	//{0x0182, 	0x00},		//
	//{0x0183, 	0x00},		//
	//{0x0184, 	0x00},		//
	//{0x0185, 	0x00},		//
	//{0x0188, 	0x00},		//
	{0x1FFD, 	0x00},		// SPI Register Unlocked
	{0x1FFE, 	0x00},		// SPI Register Unlocked
	{0x1FFF, 	0x53}		// SPI Register Unlocked
};

u8 	lmk_lock_status;
u16 lmk_regs[LMK_DEFAULT_REGS_LENGTH];

// ===========================================================================
// Local Prototype Declarations
// ---------------------------------------------------------------------------

// ===========================================================================
// External Data Declarations
// ---------------------------------------------------------------------------

// ===========================================================================
// Module Body
// ---------------------------------------------------------------------------

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_init()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_init(void) {

	u16 k;

	// Init parameters
	lmk_lock_status = FALSE;
	lmk_spi_handle = &spi_0_handle;

	// Init gpio
	hal_lmk_init_gpio();

	// Switch EMIO SPI to LMK SPI
	hal_spi_set_mux(SPI_MUX_LMK);

	// Set reference clock source
	hal_lmk_set_ref_clk_source(LMK_REF_CLK_MODEM);

	// Reset LMK device
	hal_lmk_set_gpio_reset(ENABLE);
	hal_timer_delay_usec(1000);
	hal_lmk_set_gpio_reset(DISABLE);

	// Wait for T_reset (min )
	hal_timer_delay_usec(1000);

	// Configure LMK
	for (k=0; k<LMK_DEFAULT_REGS_LENGTH; k++) {
		hal_lmk_write_reg(lmk_modem_default_cfg_regs[k][0], lmk_modem_default_cfg_regs[k][1]);
	}

	// Read back all registers
	for (k=0; k<LMK_DEFAULT_REGS_LENGTH; k++) {
		lmk_regs[k] = hal_lmk_read_reg(lmk_modem_default_cfg_regs[k][0]);
	}

	// Configure SYNC/SYSREF for JESD
	hal_lmk_cfg_sysref();

	// Wait for lock detect
	hal_timer_reload_start(LMK_LOCK_TIMEOUT);
	while(TRUE) {
		if (hal_lmk_get_gpio_lock_detect()) {
			lmk_lock_status = TRUE;
		} else if (hal_timer_check_timeout_flag()) {
			break;
		}
	}
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_init_gpio()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_init_gpio(void) {

}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_set_ref_clk_source()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_set_ref_clk_source(u32 input_clk_select) {

	if (input_clk_select == LMK_REF_CLK_RF)
		hal_dbg_set_tps(HAL_DBG_TPS_LMK_CLKIN_SEL);
	else
		hal_dbg_reset_tps(HAL_DBG_TPS_LMK_CLKIN_SEL);
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_set_gpio_reset()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_set_gpio_reset(u8 reset) {

	// Active High Signal
	if (reset)		hal_dbg_set_tps(HAL_DBG_TPS_LMK_RESET);
	else			hal_dbg_reset_tps(HAL_DBG_TPS_LMK_RESET);
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_set_gpio_sync()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_set_gpio_sync(u8 status) {

	// Active High Signal
	if (status)		hal_dbg_set_tps(HAL_DBG_TPS_LMK_SYNC);
	else			hal_dbg_reset_tps(HAL_DBG_TPS_LMK_SYNC);
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_get_gpio_lock_detect()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
u8 hal_lmk_get_gpio_lock_detect(void) {

	// TODO: Currently, Lock Detect (Status LD1/2) is not connected to PL/PS
	//       Lock status can be checked through SPI interface

	// Active High Signal

	return 0;
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_read_reg()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
u8 hal_lmk_read_reg(u16 reg_adr) {

	u8  buf[3];

	// Clear R/W, W1, W0 fields (b.15, b.14, b.13)
	reg_adr &= 0x1FFF;

	// Set R/W field
	reg_adr |= 0x8000;

	// Set tx buffer (2 byte Address + 1 byte Dummy Data)
	buf[0] = reg_adr >> 8;
	buf[1] = reg_adr & 0xFF;
	buf[2] = 0;

	// Start xmit
	hal_spi_send_data(lmk_spi_handle, buf, buf, 3, HAL_SPI_BLOCK_DISABLE);

	return buf[2];
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_write_reg()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_write_reg(u16 reg_adr, u8 reg_data) {

	u8  buf[3];

	// Clear R/W, W1, W0 fields (b.15, b.14, b.13)
	reg_adr &= 0x1FFF;

	// Set tx buffer (2 byte Address + 1 byte Data)
	buf[0] = reg_adr >> 8;
	buf[1] = reg_adr & 0xFF;
	buf[2] = reg_data;

	// Start xmit
	hal_spi_send_data(lmk_spi_handle, buf, buf, 3, HAL_SPI_BLOCK_DISABLE);
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_cfg_sysref()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_cfg_sysref(void) {

	// REF[1]. LMK04828 DATASHEET "SECTION "9.3.2 JEDEC JESD204B", dac37j84.pdf

	// Switch EMIO SPI to LMK SPI
	hal_spi_set_mux(SPI_MUX_LMK);

	// SYNC_DISSYSREF[b7]=0-"Dont Prevent the SYSREF clocks from becoming synchronized during a SYNC event", SYNC_12_DIS[b6]=0-SyncEnabled, SYNC_10_DIS[b5]=0-SyncEnabled, SYNC_8_DIS[b4]=0-SyncEnabled, SYNC_6_DIS[b3]=0-SyncEnabled, SYNC_4_DIS[b2]=0-SyncEnabled, SYNC_2_DIS[b1]=0-SyncEnabled, SYNC_0_DIS[b0]=0-SyncEnabled
	hal_lmk_write_reg(0x0144, 0x00);

	// Toggle SYNC_POL[b5] or SYNC Pin
	hal_lmk_write_reg(0x0143, 0xB1);	// SYSREF_CLR[b7]=1, SYNC_1SHOT_EN[b6]=0-Disabled, SYNC_POL[b5]=1-Inverse, SYNC_EN[b4]=1-Enabled, SYNC_PLL2_DLD[b3]=0-OFF, SYNC_PLL1_DLD[b2]=0-OFF, SYNC_MODE[b1:b0]=1-"SYNC event generated from SYNC pin"
	hal_lmk_write_reg(0x0143, 0x91);	// SYSREF_CLR[b7]=1, SYNC_1SHOT_EN[b6]=0-Disabled, SYNC_POL[b5]=0-Normal, SYNC_EN[b4]=1-Enabled, SYNC_PLL2_DLD[b3]=0-OFF, SYNC_PLL1_DLD[b2]=0-OFF, SYNC_MODE[b1:b0]=1-"SYNC event generated from SYNC pin"
	//hal_lmk_set_gpio_sync(TRUE);
	//hal_timer_delay_usec(10);
	//hal_lmk_set_gpio_sync(FALSE);

	// SYNC_DISSYSREF[b7]=1-"Prevent the SYSREF clocks from becoming synchronized during a SYNC event", SYNC_12_DIS[b6]=1-NoSyncEnabled, SYNC_10_DIS[b5]=1-NoSyncEnabled, SYNC_8_DIS[b4]=1-NoSyncEnabled, SYNC_6_DIS[b3]=1-NoSyncEnabled, SYNC_4_DIS[b2]=1-NoSyncEnabled, SYNC_2_DIS[b1]=1-NoSyncEnabled, SYNC_0_DIS[b0]=1-NoSyncEnabled
	hal_lmk_write_reg(0x0144, 0xFF);

	// Release reset of local SYSREF digital delay (SYSREF_CLR[b7]=0)
	hal_lmk_write_reg(0x0143, 0x11);	// SYSREF_CLR[b7]=0, SYNC_1SHOT_EN[b6]=0-Disabled, SYNC_POL[b5]=0-Normal, SYNC_EN[b4]=1-Enabled, SYNC_PLL2_DLD[b3]=0-OFF, SYNC_PLL1_DLD[b2]=0-OFF, SYNC_MODE[b1:b0]=1-"SYNC event generated from SYNC pin"

	// Set SYSREF operation
	hal_lmk_write_reg(0x0139, 0x02);	// SYSREF_MUX[b1:b0]=2-SYSREF Pulser
	hal_lmk_write_reg(0x0143, 0x12);	// SYNC_MODE[b1:b0]=2-"SYNC/SYSREF pulses are generated by pulser block via SYNC Pin"
	//hal_lmk_write_reg(0x139, 0x03);	// SYSREF_MUX[b1:b0]=3-SYSREF Continuous
	//hal_lmk_write_reg(0x143, 0x11);	// SYNC_MODE[b1:b0]=1-"SYNC event generated from SYNC pin"

	// Trigger SYSREF Pulser by changing SYNC pin
	//hal_lmk_set_gpio_sync(TRUE);
	//hal_timer_delay_usec(10);
	//hal_lmk_set_gpio_sync(FALSE);
}

//----------------------------------------------------------------------------
// Function Name		: hal_lmk_trigger_sysref()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_lmk_trigger_sysref(void) {

#if 1
	// REFER TO THE SECTION "9.3.2 JEDEC JESD204B" OF LMK04828 DATASHEET

	// Switch EMIO SPI to LMK SPI
	hal_spi_set_mux(SPI_MUX_LMK);

	hal_lmk_write_reg(0x0139, 0x02);	// SYSREF_MUX[b1:b0]=2-SYSREF Pulser

	// Toggle SYNC_POL[b5] or SYNC Pin
	hal_lmk_write_reg(0x0143, 0x32);
	hal_lmk_write_reg(0x0143, 0x12);

	// Trigger SYSREF Pulser by changing SYNC pin
//	hal_lmk_set_gpio_sync(TRUE);
//	hal_timer_delay_usec(10);
//	hal_lmk_set_gpio_sync(FALSE);

#else
	// Switch EMIO SPI to LMK SPI
	hal_spi_set_mux(SPI_MUX_LMK);

	hal_lmk_write_reg(0x0139, 0x03);	// SYSREF_MUX[b1:b0]=3-SYSREF Continuous

	// Toggle SYNC_POL[b5] or SYNC Pin
	//hal_lmk_write_reg(0x0143, 0x32);
	//hal_lmk_write_reg(0x0143, 0x12);
	hal_lmk_set_gpio_sync(TRUE);
	hal_timer_delay_usec(10);
	hal_lmk_set_gpio_sync(FALSE);
#endif
}

Fullscreen hal_dac.c Download

// ===========================================================================
// Include Files
// ---------------------------------------------------------------------------
#include "hal_dac.h"
#include "hal_dbg.h"
#include "hal_lmk.h"
#include "hal_pl.h"
#include "hal_spi.h"
#include "hal_timer.h"

// ===========================================================================
// External Data Definitions
// ---------------------------------------------------------------------------

// ===========================================================================
// Local Defines
// ---------------------------------------------------------------------------
#define DAC_DEFAULT_REGS_LENGTH					86

// ===========================================================================
// Local Structures
// ---------------------------------------------------------------------------

// ===========================================================================
// Local Data Definitions
// ---------------------------------------------------------------------------
SPI_HANDLE_Type	*dac_spi_handle;
u8 dac_initialized;

// Quad Channel, LMFS = 4421, HD = 0, Interpolation=1X, No Scrambling
const u16 dac_default_cfg_regs[DAC_DEFAULT_REGS_LENGTH][2] = {
	{0x4A,	0xFF1E},	// TODO: LANE_ENA[b15:b8]=0xFF-EnableLane-7/0, JESD_TEST_SEQ[b7:b6]=0-Disabled, DUAL[b5]=0-EnableDataPathCD, INIT_STATE[b4:b1]=15-?, JESD_RESET_N[b0]=0-ResetJESD
	{0x00,	0x0018},	// QMC_OFFSETAB_ENA[b15]=0-Disabled, QMC_OFFSETCD_ENA[b14]=0-Disabled, QMC_CORRAB_ENA[b3]=0-Disabled, QMC_CORRCD_ENA[b12]=0-Disabled,
						// INTERP[b11:b8]=0-1X, ALARM_ZEROS_TXENABLE_ENA[b7]=0-Disable MidLevelOutput on Alarm, OUTSUM_ENA[b6]=0-Disabled, ALARM_ZEROS_JESD_DATA_ENA[b5]=0-Disabled
						// ALARM_OUT_ENA[b4]=1-Enabled, ALARM_OUT_POL[b3]=1-Positive, PAP_ENA[b2]=0-Disabled, INV_SYNC_AB_ENA[b1]=0-Disabled, INV_SYNC_CD_ENA[b0]=0-Disabled
	{0x01,	0x0003},	// SFRAC_ENA_AB[b15]=0-Disabled, SFRAC_ENA_CD[b14]=0-Disabled, LFRAC_ENA_AB[b13]=0-Disabled, LFRAC_ENA_CD[b12]=0-Disabled
						// SFRAC_SEL_AB[b11]=0-DataB, SFRAC_SEL_D[b10]=0-DataD, DACA_COMPLIMENT[b7]=0, DACB_COMPLIMENT[b6]=0, DACC_COMPLIMENT[b5]=0, DACD_COMPLIMENT[b4]=0
	{0x02,	0x0082},	// DAC_BITWIDTH[b15:b14]=0-16bit, ZERO_INVALID_DATA[b13]=1-ZeroDataNoLink, SHORTTEST_ENA[b12]=0-Disabled
						// SIF4_ENA[b7]=1-SPI 4Wire, MIXER_ENA[b6]=0-Disabled, MIXER_GAIN[b5]=0-No 6dB gain, NCO_ENA[b4]=0-Disabled
						// TWOS[b1]=1-2s Complement, SIF_RESET[b0]=0-No SIF Reset
	{0x03,	0xF300},	// TODO: COARSE_DAC[b15:b12]=15, RESERVED[b11:b8]=3, FIFO_ERROR_ZEROS_DATA_ENA[b7]=0-Disable ZeroDataOnFifoError, SIF_TXENABLE[b0]=0-Tx Disabled
	{0x04,	0x0000},	// TODO: ALARMS_MASK[b15:b8]=0x00-MaskLaneErorrs-7/0, ALARMS_MASK[b7:b0]=0x00-MaskLaneFifoFlags-7/0
	{0x05,	0xEF03},//0xEF03},	// TODO: ALARMS_MASK[b15:b12]=0xE-MaskSYSREFErrorOnLink/3-0, ALARMS_MASK[b11:B8]=0xF-MaskAlarmPAP/A-D
	 	 	 	 	 	// ALARMS_MASK[b3]=0-MaskAlarmSERDESBLOCK0Pllock, ALARMS_MASK[b2]=0-MaskAlarmSERDESBLOCK1Pllock, ALARMS_MASK[b1]=0-MaskSYSREFSetupHoldAlarm, ALARMS_MASK[b0]=1-MaskDACPllLockAlarm
	{0x06,	0x0000},//0x0F0F},	// TODO: ALARMS_MASK[b15:b8]=0x00-MaskLaneShortTest-7/0, ALARMS_MASK[b15:b8]=0x00-MaskLaneLossSignalDetect-7/0
	{0x08,	0x0000},	// QMC_OFFSETA[b12:b0]=0 (Note: AutoSync Generated)
	{0x09,	0x0000},	// QMC_OFFSETB[b12:b0]=0
	{0x0A,	0x0000},	// QMC_OFFSETC[b12:b0]=0 (Note: AutoSync Generated)
	{0x0B,	0x0000},	// QMC_OFFSETD[b12:b0]=0
	{0x0C,	0x0400},	// QMC_GAINA[b10:b0]=0x400
	{0x0D,	0x0400},	// COARSE_MIX[b15:b12]=0-NoCoarseMixing, QMC_GAINB[b10:b0]=0x400
	{0x0E,	0x0400},	// QMC_GAINC[b10:b0]=0x400
	{0x0F,	0x0400},	// OUTPUT_DELAYAB[b15:b14]=0-0 DAC clk delay, OUTPUT_DELAYCD[b13:b12]=0-0 DAC clk delay, QMC_GAIND[b10:b0]=0x400
	{0x10,	0x0000},	// QMC_PHASEAB[b11:b0]=0 (Note: AutoSync Generated)
	{0x11,	0x0000},	// QMC_PHASECD[b11:b0]=0 (Note: AutoSync Generated)
	{0x12,	0x0000},	// PHASEOFFSETAB[b15:b0]=0 (Note: AutoSync Generated)
	{0x13,	0x0000},	// PHASEOFFSETCD[b15:b0]=0 (Note: AutoSync Generated)
	{0x14,	0x0000},	// PHASEADDAB_LWR[b15:b0]=0 NCO Freq for DACAB
	{0x15,	0x0000},	// PHASEADDAB_MID[b15:b0]=0
	{0x16,	0x0000},	// PHASEADDAB_UPR[b15:b0]=0
	{0x17,	0x0000},	// PHASEADDCD_LWR[b15:b0]=0 NCO Freq for DACCD
	{0x18,	0x0000},	// PHASEADDCD_MID[b15:b0]=0
	{0x19,	0x0000},	// PHASEADDCD_UPR[b15:b0]=0
	{0x1A,	0x0020},	// TODO: VBGR_SLEEP[b8]=0-TurnOnBandgapOverInternalR, BIASOPAMP_SLEEP[b7]=0-TurnOnBiasOpamp, TSENSE_SLEEP[b6]=0-TurnOnTempSense, PLL_SLEEP[b5]=1-TurnOffDacPLL
						// CLKRECV_SLEEP[b4]=0-TurnOnClkInReceiver, DACA_SLEEP[b3]=0-TurnOnDACA, DACB_SLEEP[b2]=0-TurnOnDACB, DACC_SLEEP[b1]=0-TurnOnDACC, DACD_SLEEP[b0]=0-TurnOnDACD
	{0x1B,	0x8000},	// TODO: EXTREF_ENA[b15]=1-ExtRef, DTEST_LANE[b14:12]=0-Lane0, DTEST[b11:b8]=0-TestDisabled NormalAlarm, ATEST[b5:b0]=0-OFF
	//{0x1C,	0x0000},	// All Reserved
	//{0x1D,	0x0000},	// All Reserved
	{0x1E,	0x9999},	// SYNCSEL_QMOFFSETAB[b15:b12]=9-AutoSync/sif_sync, SYNCSEL_QMOFFSETCD[b11:b8]=9-AutoSync/sif_sync, SYNCSEL_QMCORRAB[b7:b4]=9-AutoSync/sif_sync, SYNCSEL_QMCORRCD[b3:b0]=9-AutoSync/sif_sync
	{0x1F,	0x9980},	// SYNCSEL_MIXERAB[b15:b12]=9-AutoSync/sif_sync, SYNCSEL_MIXERCD[b11:b8]=9-AutoSync/sif_sync, SYNCSEL_NCO[b7:b4]=8-sif_sync, SIF_SYNC[b1]=0
	{0x20,	0x8008},	// TODO: SYNCSEL_DITHER[b15:12]=8-sif_sync, SYNCSEL_PAP[b7:b4]=NoSync, SYNCSEL_FIR5A[b3:b0]=8-sif_sync
	//{0x21,	0x0000},	// All Reserved
	{0x22,	0x1B1B},	// PATHA_IN_SEL[b15:14]=0-Sample0, PATHB_IN_SEL[b13:12]=1-Sample1, PATHC_IN_SEL[b11:10]=2-Sample2, PATHD_IN_SEL[b9:8]=3-Sample3,
						// PATHA_OUT_SEL[b7:b6]=0-PathA2DacA, PATHB_OUT_SEL[b5:b4]=1-PathB2DacB, PATHC_OUT_SEL[b3:b2]=2-PathC2DacC, PATHD_OUT_SEL[b1:b0]=3-PathD2DacD
	{0x23,	0x0000},//0x01FF},	// SLEEP_CNTL[b8]=1-SleepBandgapOverR, SLEEP_CNTL[b7]=1-SleepBiasOpamp, SLEEP_CNTL[b6]=1-SleepTempSensor, SLEEP_CNTL[b5]=1-SleepPLL, SLEEP_CNTL[b4]=1-SleepClkRecv
						// SLEEP_CNTL[b3]=1-SleepDacD, SLEEP_CNTL[b2]=1-SleepDacC, SLEEP_CNTL[b1]=1-SleepDacB, SLEEP_CNTL[b0]=1-SleepDacA
	{0x24,	0x0030},	// CDRVSER_SYSREF_MODE[b6:b4]=3-Skip one SYSREF pulse then use only the next one
{0x25,	0x8000},//0x0000},	// CLKJESD_DIV[b15:b13]=0-Divide-DACCLK-by-1 (JESD CLK = 400/1 = 400 MHz)
	{0x26,	0x0000},	// DITHER_ENA[b15:b12]=0-TurnOffDitherPath-D/A, DITHER_MIXER_ENA[b11:b8]=0-TurnOffFs2MixerPath-D/A, DITHER_SRA_SEL[b7:b4]=0-Max dithering
	//{0x27,	0x0000},	// All Reserved
	//{0x28,	0x0000},	// All Reserved (Note: Write to Clear)
	//{0x29,	0x0000},	// All Reserved
	//{0x2A,	0x0000},	// All Reserved
	//{0x2B,	0x0000},	// All Reserved
	//{0x2C,	0x0000},	// All Reserved
	{0x2D,	0x0001},	// PAP_DLYLEN_SEL[b3]=0-64 samples, PAP_GAIN[b2:b0]=1-DIV2
	{0x2E,	0xFFFF},	// PAP_VTH[b15:b0]=0xFFFF- Max threshold
	{0x2F,	0x0004},//0x0004},	// TODO: TITEST_DIEID_READ_ENA[b14]=0-Disabled, RESERVED[b2]=1, SIFDAC_ENA[b0]=0-DisableDacOutput (Dac outputs are set to SIFDAC value when enabled)
	{0x30,	0x4000},	// SIFDAC[b15:b0]=16384 (half for debug!!!)
	{0x31,	0x1000},	// LOCKDET_ADJ[b15:13]=0, PLL_RESET[b12]=1-Reset, PLL_NDIVSYNC_ENA[b11]=0, PLL_ENA[b10]=0-DisablePll, PLL_CP[b9:b8]=0, PLL_N[b7:b3]=0-DIV1, MEMIN_PLL_LFVOLT[b2:b0]= (ReadOnly)
	{0x32,	0x0000},	// PLL_M[b15:b8]=0-DIV1, PLL_P[b7:b4]=0-DIV2
	{0x33,	0x0000},	// PLL_VCOSEL[b15]=0-VCO_5GHz, PLL_VCO[b14:b9]=0-Fmin, PLL_VCOITUNE[b8:b7]=2-9.8mA, PLL_CP_ADJ[b6:b2]=0-LPFTerminal=0V
	{0x34,	0x0000},	// TODO: SYNCB_LVDS_LOPWRB[b15]=0, SYNCB_LVDS_LOPWRA[b14]=0, SYNCB_LVDS_LPSEL[b13]=0-100Ohm, SYNCB_LVDS_EFFUSE_SEL[b12]=0-Disabled, SYNCB_LVDS_SLEEP[b8]=0-NoSleep, SYNCB_LVDS_SUB_ENA[b7]=0-1V2 common mode
	//{0x35,	0x0000},	// All Reserved
	//{0x36,	0x0000},	// All Reserved
	//{0x37,	0x0000},	// All Reserved
	//{0x38,	0x0000},	// All Reserved
	//{0x39,	0x0000},	// All Reserved
	//{0x3A,	0x0000},	// All Reserved
	{0x3B,	0x0000},	// SERDES_CLK_SEL[15]=0-DACCLK, SERDES_REFCLK_DIV[b14:b11]=0-DIV1 (SERDES REF CLK = 400/1 = 400 MHz)
	{0x3C,	0x8228},	// TODO: RW_CFGPLL[b15]=1-EnableENDIVCLK(PLL_out/5), RW_CFGPLL[b12:b11]=0-MediumLoopBW, RW_CFGPLL[b10]=0-TurnOnPLL, RW_CFGPLL[b9]=1-VRANGE VCO<2.17, RW_CFGPLL[b8:b1]=20-MPY_5x
	{0x3D,	0x0088},	// TODO: RW_CFGRX0[b14:b12]=0-TESTPATT_Disabled, RW_CFGRX0[b7]=1-ENOC_Enable OffsetCompensation, RW_CFGRX0[b6]=0-EQHLD_EqualizerAdaptationEnabled, RW_CFGRX0[b5:b3]=1-EQ_FullyAdaptive, RW_CFGRX0[b2:b0]=0-CDR
	{0x3E,	0x0108},	// TODO: RW_CFGRX0[b15:b13]=0-LOS_?, RW_CFGRX0[b10:b8]=1-TERM_0V7, RW_CFGRX0[b6:b5]=0-RATE_Full, RW_CFGRX0[b4:b2]=2-BUSWIDTH_, RW_CFGRX0[b1]=0-SLEEPRX_?
	{0x3F,	0x0000},	// INVPAIR[b7:b0]=0x00
	//{0x40,	0x0000},	// All Reserved
	//{0x45,	0x0000},	// All Reserved
	//{0x46,	0x214C},//0x0044},	// LID0[b15:b11]=4-JESDID for Lane0, LID1[b10:b6]=5-JESDID for Lane1, LID2[b5:b1]=6-JESDID for Lane2
	//{0x47,	0x3802},//0x190A},	// LID3[b15:b11]=7-JESDID for Lane3, LID4[b10:b6]=0-JESDID for Lane4, LID5[b5:b1]=1-JESDID for Lane5
	//{0x48,	0x10C3},//0x31C3},	// LID6[b15:b11]=2-JESDID for Lane6, LID7[b10:b6]=3-JESDID for Lane7, SUBCLASSV[b1]=1-SUBCLASS1, JESDV[b0]=1-JESD204B
	{0x46,	0x0044},	// LID0[b15:b11]=4-JESDID for Lane0, LID1[b10:b6]=5-JESDID for Lane1, LID2[b5:b1]=6-JESDID for Lane2
	{0x47,	0x190A},	// LID3[b15:b11]=7-JESDID for Lane3, LID4[b10:b6]=0-JESDID for Lane4, LID5[b5:b1]=1-JESDID for Lane5
	{0x48,	0x31C3},	// LID6[b15:b11]=2-JESDID for Lane6, LID7[b10:b6]=3-JESDID for Lane7, SUBCLASSV[b1]=1-SUBCLASS1, JESDV[b0]=1-JESD204B

	{0x49,	0x0000},	// LINK_ASSIGN[b15:b14]=0-link0 for Lane7, LINK_ASSIGN[b13:b12]=0-link0 for Lane6, LINK_ASSIGN[b11:b10]=0-link0 for Lane5, LINK_ASSIGN[b9:b8]=0-link0 for Lane4
						// LINK_ASSIGN[b7:b6]=0-link0 for Lane3, LINK_ASSIGN[b5:b4]=0-link0 for Lane2, LINK_ASSIGN[b3:b2]=0-link0 for Lane1, LINK_ASSIGN[b1:b0]=0-link0 for Lane0
	{0x4A,	0xFF1E},	// TODO: LANE_ENA[b15:b8]=0xFF-EnableLane-7/0, JESD_TEST_SEQ[b7:b6]=0-Disabled, DUAL[b5]=0-EnableDataPathCD, INIT_STATE[b4:b1]=15-?, JESD_RESET_N[b0]=0-ResetJESD
	{0x4B,	0x0801},	// TODO: RBD_M1[b12:b8]=8 (<= k_m1), F_M1[b7:b0]=1-2 octet per frame
	{0x4C,	0x0F03},	// K_M1[b12:b8]=15-16 MultiFrame, L_M1[b4:b0]=3-4 Lane used
	{0x4D,	0x0300},	// M_M1[b12:b8]=3-4 Converter, S_M1[b4:b0]=0-1 sample per frame
	{0x4E,	0x0F0F},	// NPRIME_M1[b12:b8]=15, HD[b6]=0-DisableHighDensity, SCR[b5]=0-Disable Scrambler, N_M1[b4:b0]=15
	{0x4F,	0x1C61},	// TODO: MATCH_DATA[b15:b8]0x1C (/R/=/K28.0/), MATCH_SPECIFIC[b7]=0, MATCH_CTRL[b6]=1, NO_LANE_SYNC[b5]=1-?, JESD_COMMAALIGN_ENA[b0]=1
	{0x50,	0x0000},	// ADJCNT_LINK0[b15:b12]=0, ADJDIR_LINK0[b11]=0, BID_LINK0[b10:b7]=0, CF_LINK0[b6:b2]=0, CS_LINK0[b1:b0]=0
	{0x51,	0x00FF},	// DID_LINK0[b15:b8]=0, SYNC_REQUEST_ENA_LINK0[b7:b0]=0xFF-SyncReqonErrors
	{0x52,	0x00FF},	// DISABLE_ERR_REPORT_LINK0[b9]=0-ReportErrorOn SYNC_N, PHADJ_LINK0[b8]=0, ERROR_ENA_LINK0[b7:b0]=0xFF-
	{0x53,	0x0000},	// ADJCNT_LINK1[b15:b12]=0, ADJDIR_LINK1[b11]=0, BID_LINK1[b10:b7]=0, CF_LINK1[b6:b2]=0, CS_LINK1[b1:b0]=0
	{0x54,	0x00FF},	// DID_LINK1[b15:b8]=0, SYNC_REQUEST_ENA_LINK1[b7:b0]=0xFF-SyncReqonErrors
	{0x55,	0x00FF},	// DISABLE_ERR_REPORT_LINK1[b9]=0-ReportErrorOn SYNC_N, PHADJ_LINK1[b8]=0, ERROR_ENA_LINK1[b7:b0]=0xFF-
	{0x56,	0x0000},	// ADJCNT_LINK2[b15:b12]=0, ADJDIR_LINK2[b11]=0, BID_LINK2[b10:b7]=0, CF_LINK2[b6:b2]=0, CS_LINK2[b1:b0]=0
	{0x57,	0x00FF},	// DID_LINK2[b15:b8]=0, SYNC_REQUEST_ENA_LINK2[b7:b0]=0xFF-SyncReqonErrors
	{0x58,	0x00FF},	// DISABLE_ERR_REPORT_LINK2[b9]=0-ReportErrorOn SYNC_N, PHADJ_LINK2[b8]=0, ERROR_ENA_LINK2[b7:b0]=0xFF-
	{0x59,	0x0000},	// ADJCNT_LINK3[b15:b12]=0, ADJDIR_LINK3[b11]=0, BID_LINK3[b10:b7]=0, CF_LINK3[b6:b2]=0, CS_LINK3[b1:b0]=0
	{0x5A,	0x00FF},	// DID_LINK3[b15:b8]=0, SYNC_REQUEST_ENA_LINK3[b7:b0]=0xFF-SyncReqonErrors
	{0x5B,	0x00FF},	// DISABLE_ERR_REPORT_LINK3[b9]=0-ReportErrorOn SYNC_N, PHADJ_LINK3[b8]=0, ERROR_ENA_LINK3[b7:b0]=0xFF-
	{0x5C,	0x0055},	// ERR_CNT_CLR_LINK3[b15]=0-NoClearErrorCount, SYSREF_MODE_LINK3[b14:b12]=0-Don�t use SYSREF pulse, ERR_CNT_CLR_LINK2[b11]=0-NoClearErrorCount, SYSREF_MODE_LINK2[b10:b8]=0-Don�t use SYSREF pulse
						// ERR_CNT_CLR_LINK1[b7]=0-NoClearErrorCount, SYSREF_MODE_LINK1[b6:b4]=5-Skip two SYSREF pulses then use only the next on, ERR_CNT_CLR_LINK0[b3]=0-NoClearErrorCount, SYSREF_MODE_LINK0[b2:b0]=5-Skip two SYSREF pulses then use only the next on
	//{0x5D,	0x0000},	// All Reserved
	{0x5E,	0x0000},	// All Reserved
	{0x5F,	0x0123},	// OCTETPATH_SEL(0)[b14:b12]=4-SERDES Lane4 for JESD Lane0, OCTETPATH_SEL(1)[b10:b8]=5-SERDES Lane5 for JESD Lane1, OCTETPATH_SEL(2)[b6:b4]=6-SERDES Lane6 for JESD Lane2, OCTETPATH_SEL(0)[b2:b0]=7-SERDES Lane7 for JESD Lane3
	{0x60,	0x4567},	// OCTETPATH_SEL(4)[b14:b12]=0-SERDES Lane0 for JESD Lane4, OCTETPATH_SEL(5)[b10:b8]=1-SERDES Lane1 for JESD Lane5, OCTETPATH_SEL(6)[b6:b4]=2-SERDES Lane2 for JESD Lane6, OCTETPATH_SEL(7)[b2:b0]=3-SERDES Lane3 for JESD Lane7

	{0x61,	0x0111},	// SYNCN_POL[b15]=0-?, SYNCNCD_SEL[b11:b8]=1-Link0 SYNC_N outputs ANDed for SYNC_N_CD, SYNCNAB_SEL[b7:b4]=1-Link0 SYNC_N outputs ANDed for SYNC_N_AB, SYNCN_SEL[b3:b0]=1-Link0 SYNC_N outputs ANDed for SYNCB
	//{0x62,	0x0000},	// All Reserved
	//{0x63,	0x0000},	// All Reserved
	{0x64,	0x0000},	// ALARM_I_ERROR(0)[b15:b8]=0, ALARM_FIFO_FLAGS(0)[b3:b0]=0 (Note: Write to Clear)
	{0x65,	0x0000},	// ALARM_I_ERROR(1)[b15:b8]=0, ALARM_FIFO_FLAGS(1)[b3:b0]=0 (Note: Write to Clear)
	{0x66,	0x0000},	// ALARM_I_ERROR(2)[b15:b8]=0, ALARM_FIFO_FLAGS(2)[b3:b0]=0 (Note: Write to Clear)
	{0x67,	0x0000},	// ALARM_I_ERROR(3)[b15:b8]=0, ALARM_FIFO_FLAGS(3)[b3:b0]=0 (Note: Write to Clear)
	{0x68,	0x0000},	// ALARM_I_ERROR(4)[b15:b8]=0, ALARM_FIFO_FLAGS(4)[b3:b0]=0 (Note: Write to Clear)
	{0x69,	0x0000},	// ALARM_I_ERROR(5)[b15:b8]=0, ALARM_FIFO_FLAGS(5)[b3:b0]=0 (Note: Write to Clear)
	{0x6A,	0x0000},	// ALARM_I_ERROR(6)[b15:b8]=0, ALARM_FIFO_FLAGS(6)[b3:b0]=0 (Note: Write to Clear)
	{0x6B,	0x0000},	// ALARM_I_ERROR(7)[b15:b8]=0, ALARM_FIFO_FLAGS(7)[b3:b0]=0 (Note: Write to Clear)
	{0x6C,	0x0000},	// ALARM_SYSREF_ERR[b15:b12]=0, ALARM_PAP[b11:b8]=0, ALARM_RW0_PLL[b3]=0, ALARM_RW1_PLL[b2]=0, ALARM_FROM_PLL[b0]=0
	{0x6D,	0x0000}		// ALARM_FROM_SORTTEST[b15:b8]=0, MEMIN_RW_LOSDCT[b7:B0]=0
//	{0x6E,	0x0000},	// SFRAC_COEF0_AB[b15:b14]=0, SFRAC_COEF1_AB[b13:b9]=0, SFRAC_COEF2_AB[b8:b1]=0
//	{0x6F,	0x0000},	// SFRAC_COEF3_AB[b9:b0]=0
//	{0x70,	0x0000},	// SFRAC_COEF4_AB(15:10)[b15:b0]=0
//	{0x71,	0x0000},	// SFRAC_COEF4_AB(18:16)[b15:b13]=0, SFRAC_COEF5_AB[b9:b0]=0
//	{0x72,	0x0000},	// SFRAC_COEF6_AB[b8:b0]=0
//	{0x73,	0x0000},	// SFRAC_COEF7_AB[b15:b9]=0, SFRAC_COEF8_AB[b8:b4]=0, SFRAC_COEF9_AB[b3:b2]=0
//	{0x74,	0x0000},	// SFRAC_INVGAIN_AB(15:0)[b15:b0]=0
//	{0x75,	0x0000},	// SFRAC_INVGAIN_AB(19:16)[b15:b12]=0, LFRAC_COEFSEL_A[b5:b3]=0, LFRAC_COEFSEL_B[b2:b0]=0
//	{0x76,	0x0000},	// SFRAC_COEF0_CD[b15:b14]=0, SFRAC_COEF1_CD[b13:b9]=0, SFRAC_COEF2_CD[b8:b1]=0
//	{0x77,	0x0000},	// SFRAC_COEF3_CD[b9:b0]=0
//	{0x78,	0x0000},	// SFRAC_COEF4_CD(15:10)[b15:b0]=0
//	{0x79,	0x0000},	// SFRAC_COEF4_CD(18:16)[b15:b13]=0, SFRAC_COEF5_CD[b9:b0]=0
//	{0x7A,	0x0000},	// SFRAC_COEF6_CD[b8:b0]=0
//	{0x7B,	0x0000},	// SFRAC_COEF7_CD[b15:b9]=0, SFRAC_COEF8_CD[b8:b4]=0, SFRAC_COEF9_CD[b3:b2]=0
//	{0x7C,	0x0000},	// SFRAC_INVGAIN_CD(15:0)[b15:b0]=0
//	{0x7D,	0x0000},	// SFRAC_INVGAIN_CD(19:16)[b15:b12]=0, LFRAC_COEFSEL_C[b5:b3]=0, LFRAC_COEFSEL_D[b2:b0]=0
	//{0x7E,	0x0000},	// All Reserved
};


u16 dac_regs[DAC_DEFAULT_REGS_LENGTH];

u32 reg_jesd_tx[2];
u32 reg_jesd_tx_2;
u32 reg_dac[10];

u8  dac_tps_0 = 255;
u8  dac_tps_1 = 0;
u8  dac_tps_2 = 1;
u8  dac_tps_3 = 16;

// ===========================================================================
// Local Prototype Declarations
// ---------------------------------------------------------------------------

// ===========================================================================
// External Data Declarations
// ---------------------------------------------------------------------------

// ===========================================================================
// Module Body
// ---------------------------------------------------------------------------

//----------------------------------------------------------------------------
// Function Name		: hal_dac_init()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_init(void) {

	u16 k, reg;
	u16 alarm_lane[DAC_LANE_COUNT], alarm_common, alarm_short_los;
	u16 error_count_link[DAC_LINK_COUNT];
	u8  alarm_gpio;

	// REFER TO THE SECTION "8.3 INITIALIZATION SET UP" of DAC37J84 DATASHEET

	// Init parameters
	dac_spi_handle = &spi_0_handle;

	// Init gpio
	hal_dac_init_gpio();

	// Switch EMIO SPI to DAC SPI
	hal_spi_set_mux(SPI_MUX_DAC);

	// Disable SLEEP
	hal_dac_set_gpio_sleep(DISABLE);

	// Disable TXENABLE
	hal_dac_set_gpio_tx_enable(DISABLE);

	// DACCLK should be ready at this point!

	// Reset DAC device / SIF registers (min pulse width 25 ns)
	hal_dac_set_gpio_reset(ENABLE);
	hal_timer_delay_usec(500);
	hal_dac_set_gpio_reset(DISABLE);

	// Wait for T_reset (min ?)
	hal_timer_delay_usec(1000);

	for (k=0; k<DAC_DEFAULT_REGS_LENGTH; k++) {
		hal_dac_write_reg(dac_default_cfg_regs[k][0], dac_default_cfg_regs[k][1]);
	}

	// Read back all registers
	for (k=0; k<DAC_DEFAULT_REGS_LENGTH; k++) {
		dac_regs[k] = hal_dac_read_reg(dac_default_cfg_regs[k][0]);
	}

	// STEP-5: Verify the SERDES PLL lock status by checking the SERDES PLL alarms: alarm_rw0_pll[b3] (alarm for lanes 0
	// through 3) and alarm_rw1_pll[b2] (alarm for lanes 4 through 7). Clear alarms before monitoring
	hal_timer_delay_usec(10);
	hal_dac_read_alarm(TRUE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
	alarm_gpio = hal_dac_get_gpio_alarm();

	// STEP-6: Reset DAC JESD Core (INIT_STATE[b4:b1]=F-?, JESD_RESET_N[b0]=0-ResetJESD)
	reg = hal_dac_read_reg(0x4A);
	reg &= 0xFFE0;
	reg |= 0x001E;
	hal_dac_write_reg(0x4A,	reg);

	// According to document: At this point, SYNCB is held in HIGH and "alarm_sysref_err[b15:b12] of Reg-0x6C is active.

	// Update alarms
	hal_dac_read_alarm(TRUE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
	alarm_gpio = hal_dac_get_gpio_alarm();

	// STEP-11:Set Reg-0x4A with INIT_STATE[b4:b1]=F-?, JESD_RESET_N[b0]=1-ReleaseResetJESD
	reg = hal_dac_read_reg(0x4A);
	reg &= 0xFFE0;
	reg |= 0x001F;
	hal_dac_write_reg(0x4A,	reg);

	// STEP-12:Set Reg-0x4A with INIT_STATE[b4:b1]=0-initial, JESD_RESET_N[b0]=1-ReleaseResetJESD
	reg = hal_dac_read_reg(0x4A);
	reg &= 0xFFE0;
	reg |= 0x0001;
	hal_dac_write_reg(0x4A,	reg);

	// STEP-13: Update alarms
	hal_dac_read_alarm(TRUE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
	alarm_gpio = hal_dac_get_gpio_alarm();

	// STEP-14: Start SYSREF generation at this point
	hal_lmk_trigger_sysref();

	// Wait enough time
	hal_timer_delay_usec(1000);

	// STEP-16: Clear alarms, then wait for app. 1-2 us and check values
	hal_dac_read_alarm(TRUE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
	alarm_gpio = hal_dac_get_gpio_alarm();

	// Enable Xmit by asserting TXENABLE or setting sif_txenable to 1
	hal_dac_set_gpio_tx_enable(ENABLE);

	dac_initialized = TRUE;
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_init_gpio()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_init_gpio(void) {

}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_set_gpio_reset()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_set_gpio_reset(u8 status) {

	// Active Low Signal
	if (status)		hal_dbg_reset_tps(HAL_DBG_TPS_DAC_RESETB);
	else			hal_dbg_set_tps(HAL_DBG_TPS_DAC_RESETB);
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_set_gpio_sleep()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_set_gpio_sleep(u8 status) {

	// Active High Signal
	if (status)		hal_dbg_set_tps(HAL_DBG_TPS_DAC_SLEEP);
	else			hal_dbg_reset_tps(HAL_DBG_TPS_DAC_SLEEP);
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_set_gpio_tx_enable()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_set_gpio_tx_enable(u8 status) {

	// Active High Signal
	if (status)		hal_dbg_set_tps(HAL_DBG_TPS_DAC_TXENABLE);
	else			hal_dbg_reset_tps(HAL_DBG_TPS_DAC_TXENABLE);
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_get_gpio_alarm()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
u8 hal_dac_get_gpio_alarm(void) {

	u8 alarm = FALSE;

	// TODO: Active High Signal

	return alarm;
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_read_reg()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
u16 hal_dac_read_reg(u8 reg_adr) {

	u8  buf[3];
	u16 reg;

	// Set R/W (b.7)
	reg_adr |= 0x80;

	// Set tx buffer (1 byte Address + 2 byte Dummy Data)
	buf[0] = reg_adr;
	buf[1] = 0;
	buf[2] = 0;

	// Start xmit
	hal_spi_send_data(dac_spi_handle, buf, buf, 3, HAL_SPI_BLOCK_DISABLE);

	reg = buf[1];
	reg <<= 8;
	reg |= buf[2];

	return reg;
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_write_reg()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_write_reg(u8 reg_adr, u16 reg_data) {

	u8  buf[3];

	// Clear R/W (b.7)
	reg_adr &= 0x7F;

	// Set tx buffer (1 byte Address + 2 byte Data)
	buf[0] = reg_adr;
	buf[1] = reg_data >> 8;
	buf[2] = reg_data & 0xFF;

	// Start xmit
	hal_spi_send_data(dac_spi_handle, buf, buf, 3, HAL_SPI_BLOCK_DISABLE);
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_prbs_test()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_prbs_test(u16 test_lane, u16 prbs_pattern) {

	u16 reg;
	u16 alarm_lane[DAC_LANE_COUNT], alarm_common, alarm_short_los;
	u16 error_count_link[DAC_LINK_COUNT];
	u8  loop = TRUE;

	// To run the PRBS test on the DAC, users first need to setup the DAC for normal use,
	// then make the following SPI writes:
	//
	// 1. config74, set bits 4:0 to 0x1E to disable JESD clock.
	// 2. config61, set bits 14:12 to 0x2 to enable the 7-bit PRBS test pattern; or set bits 14:12 to 0x3 to enable the
	// 	  23-bit PRBS test pattern; or set bits 14:12 to 0x4 to enable the 31-bit PRBS test pattern.
	// 3. config27, set bits 11:8 to 0x3 to output PRBS test fail on ALARM terminal.
	// 4. config27, set bits 14:12 to the lane to be tested (0 through 7).
	// 5. config62, make sure bits 12:11 are set to 0x0 to disable character alignment.
	//
	// Users should monitor the ALARM terminal to see the results of the test. If the test is failing, ALARM will be high
	// (or toggling if marginal). If the test is passing, the ALARM will be low.

	if (dac_initialized) {

		// Switch EMIO SPI to DAC SPI
		hal_spi_set_mux(SPI_MUX_DAC);

		// Disable JESD clock.
		reg = hal_dac_read_reg(0x4A);
		reg &= 0xFFE0;
		reg |= 0x1E;
		hal_dac_write_reg(0x4A, reg);

		// Set TESTPATT (b[12:11]=PRBS Pattern)
		reg = hal_dac_read_reg(0x3D);
		reg &= 0x8FFF;
		reg |= (prbs_pattern << 12);
		hal_dac_write_reg(0x3D, reg);

		// Set DTEST to TESTFAIL on ALARM terminal and set DTEST_LANE to the lane to be tested (b[14:12]=dtest_lane, b[11:8]=3-TESTFAIL)
		reg = hal_dac_read_reg(0x1B);
		reg &= 0x80FF;
		reg |= 0x0300;
		reg |= (test_lane << 12);
		hal_dac_write_reg(0x1B, reg);

		// Disable character alignment (b[12:11]=0)
		reg = hal_dac_read_reg(0x3E);
		reg &= 0xE7FF;
		hal_dac_write_reg(0x3E, reg);

		// Check ALARM signal and read all alarms
		hal_dac_read_alarm(TRUE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
		while (loop) {
			hal_dac_read_alarm(FALSE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
		}
	}
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_read_alarm()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_read_alarm(u16 clear_alarm, u16 *alarm_lane, u16 *alarm_common, u16 *alarm_short_los, u16 *error_count_link) {

	u16 k;

	// Switch EMIO SPI to DAC SPI
	hal_spi_set_mux(SPI_MUX_DAC);

	// Clear Alarms
	if (clear_alarm) {
		hal_dac_write_reg(0x6C, 0x0000);
		hal_dac_write_reg(0x6D, 0x0000);
		for (k=0; k<DAC_LANE_COUNT; k++)
			hal_dac_write_reg(0x64+k, 0x0000);

		// Wait for enough time
		hal_timer_delay_usec(100);

		*alarm_common = 0;
		*alarm_short_los = 0;
		for (k=0; k<DAC_LANE_COUNT; k++)
			alarm_lane[k] = 0;
		for (k=0; k<DAC_LINK_COUNT; k++)
			error_count_link[k] = 0;
	}

	// Read Alarms
	*alarm_common = hal_dac_read_reg(0x6C);
	*alarm_short_los = hal_dac_read_reg(0x6D);
	for (k=0; k<DAC_LANE_COUNT; k++)
		alarm_lane[k] = hal_dac_read_reg(0x64+k);

	// Get Link Error Count (Link Error Count can be reset on JESD synchronization or by toggling err_cnt_clr_linkX of Reg_0x5C)
	for (k=0; k<DAC_LINK_COUNT; k++)
		error_count_link[k] = hal_dac_read_reg(0x41+k);
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_init_jesd()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_init_jesd(void) {

	u16 dac_alarm_lane[DAC_LANE_COUNT], dac_alarm_common, dac_alarm_short_los;
	u16 dac_error_count_link[DAC_LINK_COUNT];
	u8  dac_alarm_gpio;
	u16 dac_reg_adr, dac_reg;
	u8  dac_reset_alarm = FALSE;
	u8  link_layer_test_enable = FALSE;
	u8  link_layer_test_id = 1;
	u8  prbs_test_enable = FALSE;
	u32 drp_reg, k;

	hal_pl_hw_set_tps_1_mux(dac_tps_1);
	hal_pl_hw_set_tps_2_mux(dac_tps_2);
	hal_pl_hw_set_tps_3_mux(dac_tps_3);

	// Init DAC
	//hal_pl_hw_set_jesd_reset(TRUE);
	//hal_dac_init();
	//hal_pl_hw_set_jesd_reset(FALSE);

	// Get JESD TX IP Version
	reg_jesd_tx[0] = hal_pl_read_reg(PL_JESD_TX_REG_VERSION_ADR);

	// Reset JESD TX IP ([b16]=1-Disable Watchdog Timer, [b0]=1-Reset in progress)
	hal_pl_hw_set_jesd_reset(1);
	hal_timer_delay_usec(200);
	hal_pl_hw_set_jesd_reset(0);
	hal_pl_write_reg(PL_JESD_TX_REG_RESET_ADR, 0x00010001);
	while (hal_pl_read_reg(PL_JESD_TX_REG_RESET_ADR) & 0x00000001) {}

	// Set ILA Support ([b0]=1-Enable)
	hal_pl_write_reg(PL_JESD_TX_REG_ILA_SUPPORT_ADR, 1);

	// Set SUBCLASS ([b1:b0]=1-Subclass1
	hal_pl_write_reg(PL_JESD_TX_REG_SUBCLASS_MODE_ADR, 1);

	// Set SYSREF ([b16]=1-Sysref Req on Resync, [b0]=1-Sysref Always)
	hal_pl_write_reg(PL_JESD_TX_REG_SYSREF_ADR, 0x00010001);
	//hal_pl_write_reg(PL_JESD_TX_REG_SYSREF_ADR, 0x00010000);

	// Set Test Mode ([b2:b0]=0-Normal / 1-K28.5 / 2-ILA Seq / 3-D21.5 / 4-RPAT / 5-JSPAT)
	hal_pl_write_reg(PL_JESD_TX_REG_TEST_MODES_ADR, 0);
	//hal_pl_write_reg(PL_JESD_TX_REG_TEST_MODES_ADR, 2);
	//hal_pl_hw_set_jesd_phy_prbsel(JESD_PHY_PRBSEL_D21P5);

	#if HAL_DAC_JESD_CFG_QUAD_LMFS4421_HD0_K16_SCRAMBLINGOFF
		// Set Lanes In Use (b[4-0]:3-4 Lanes)
		hal_pl_write_reg(PL_JESD_TX_REG_LANES_IN_USE_ADR, 3);
		// Set Scrambling (b[0]:0-Disable Scrambling)
		hal_pl_write_reg(PL_JESD_TX_REG_SCRAMBLING_ADR, 0);
		// Set F = 2
		hal_pl_write_reg(PL_JESD_TX_REG_OCTET_PER_FRAME_ADR, 1);
		// Set K = 16
		hal_pl_write_reg(PL_JESD_TX_REG_FRAME_PER_MULTIFRAME_ADR, 15);
		// Set ILA MultiFrame = 4
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_MULTIFRAMES_ADR, 3);
		// Set ILA CFG DATA-3 (b[11-8]:0-Bank ID, b[7-0]:0-Device ID)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_3_ADR, 0x00000000);
		// Set ILA CFG DATA-4 (b[25-24]:0-CS, b[20-16]:15-N', b[12-8]:15-N, b[7-0]:4-M)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_4_ADR, 0x000F0F04);
		// Set ILA CFG DATA-5 (b[28-24]:0-CF, b[16]:0-HD, b[12-8]:1-S)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_5_ADR, 0x00000100);
		// Set ILA CFG DATA-6 (b[15-8]:0-RES2, b[7-0]:0-RES1)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_6_ADR, 0);
		// Set ILA CFG DATA-7 (Subclass2 Only, b[16]:0-ADJDIR, b[8]:0-PHADJ, b[3-0]:0-ADJCNT)
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_7_ADR, 0x0000);

	#elif HAL_DAC_JESD_CFG_DUAL_LMFS2221_HD0_K16_SCRAMBLINGOFF
		// Set Lanes In Use (b[4-0]:1-2 Lanes)
		hal_pl_write_reg(PL_JESD_TX_REG_LANES_IN_USE_ADR, 1);
		// Set Scrambling (b[0]:0-Disable Scrambling)
		hal_pl_write_reg(PL_JESD_TX_REG_SCRAMBLING_ADR, 0);
		// Set F = 2
		hal_pl_write_reg(PL_JESD_TX_REG_OCTET_PER_FRAME_ADR, 1);
		// Set K = 16
		hal_pl_write_reg(PL_JESD_TX_REG_FRAME_PER_MULTIFRAME_ADR, 15);
		// Set ILA MultiFrame = 4
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_MULTIFRAMES_ADR, 3);
		// Set ILA CFG DATA-3 (b[11-8]:0-Bank ID, b[7-0]:0-Device ID)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_3_ADR, 0x00000000);
		// Set ILA CFG DATA-4 (b[25-24]:0-CS, b[20-16]:15-N', b[12-8]:15-N, b[7-0]:2-M)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_4_ADR, 0x000F0F02);
		// Set ILA CFG DATA-5 (b[28-24]:0-CF, b[16]:0-HD, b[12-8]:1-S)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_5_ADR, 0x00000100);
		// Set ILA CFG DATA-6 (b[15-8]:0-RES2, b[7-0]:0-RES1)
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_6_ADR, 0);
		// Set ILA CFG DATA-7 (Subclass2 Only, b[16]:0-ADJDIR, b[8]:0-PHADJ, b[3-0]:0-ADJCNT)
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_7_ADR, 0x0000);

	#else // HAL_DAC_JESD_CFG_DUAL_LMFS2221_HD0_K16_SCRAMBLINGOFF
		// Set Lanes In Use ([b4:b0]=1-2 Lanes)
		hal_pl_write_reg(PL_JESD_TX_REG_LANES_IN_USE_ADR, 3);
		// Set Scrambling ([b0]=0-Disable Scrambling)
		hal_pl_write_reg(PL_JESD_TX_REG_SCRAMBLING_ADR, 0);
		// Set F = 2
		hal_pl_write_reg(PL_JESD_TX_REG_OCTET_PER_FRAME_ADR, 1);
		// Set K = 16
		hal_pl_write_reg(PL_JESD_TX_REG_FRAME_PER_MULTIFRAME_ADR, 15);
		// Set ILA MultiFrame = 4
		hal_pl_write_reg(PL_JESD_TX_REG_ILA_MULTIFRAMES_ADR, 3);
		// Set ILA CFG DATA-3 (b[11-8]:0-Bank ID, b[7-0]:0-Device ID)
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_3_ADR, 0x00000005);
		// Set ILA CFG DATA-4 (b[25-24]:0-CS, b[20-16]:15-N', b[12-8]:15-N, b[7-0]:3-M)
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_4_ADR, 0x000F0F03);
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_4_ADR, 0x00101004);
		// Set ILA CFG DATA-5 (b[28-24]:0-CF, b[16]:0-HD, b[12-8]:0-S)
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_5_ADR, 0x00000000);
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_5_ADR, 0x00010000);
		// Set ILA CFG DATA-6 (b[15-8]:0-RES2, b[7-0]:0-RES1)
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_6_ADR, 0);
		// Set ILA CFG DATA-7 (Subclass2 Only, b[16]:0-ADJDIR, b[8]:0-PHADJ, b[3-0]:0-ADJCNT)
		//hal_pl_write_reg(PL_JESD_TX_REG_ILA_CFG_DATA_7_ADR, 0x0000);
	#endif

	hal_pl_hw_set_tps_1_mux(dac_tps_1);
	hal_pl_hw_set_tps_2_mux(dac_tps_2);
	hal_pl_hw_set_tps_3_mux(dac_tps_3);

	// Get Sync Status ([b16]:1-Sysref Captured, [b0]:1-Link Sync)
	reg_jesd_tx[1] = hal_pl_read_reg(PL_JESD_TX_REG_SYNC_STATUS_ADR);

	// Init DAC
	hal_dac_init();
	// Trigger SYSREF for ADC/DAC JESD Interface
	hal_lmk_trigger_sysref();

	// Switch EMIO SPI to DAC SPI
	hal_spi_set_mux(SPI_MUX_DAC);

	//
	//hal_pl_hw_set_jesd_phy_prbsel(1);
	//hal_pl_hw_set_jesd_tx_prbsel(1);

	dac_reg_adr = 0x00;
	while (1) {
		// Get Sync Status ([b16]=1-Sysref Captured, [b0]=1-Link Sync)
		reg_jesd_tx[1] = hal_pl_read_reg(PL_JESD_TX_REG_SYNC_STATUS_ADR);

		// Clear alarms, then wait for app. 1-2 us and check values
		hal_dac_read_alarm(dac_reset_alarm, dac_alarm_lane, &dac_alarm_common, &dac_alarm_short_los, dac_error_count_link);
		dac_reset_alarm = FALSE;
		hal_timer_delay_usec(100);
		dac_alarm_gpio = hal_dac_get_gpio_alarm();

		// Read DAC register
		dac_reg = hal_dac_read_reg(dac_reg_adr);

		hal_pl_hw_set_tps_1_mux(dac_tps_1);
		hal_pl_hw_set_tps_2_mux(dac_tps_2);
		hal_pl_hw_set_tps_3_mux(dac_tps_3);

		//hal_dac_set_gpio_tx_enable(DISABLE);
		//hal_dac_set_gpio_tx_enable(ENABLE);

//		for (k=0x30; k<0x38; k++)
//			drp_reg = hal_jesd_phy_drp_get_reg(0, 0, k);

		hal_adc_init_jesd_phy();

		if (link_layer_test_enable) {
			link_layer_test_enable = FALSE;
			hal_pl_hw_set_jesd_reset(1);
			hal_pl_hw_set_jesd_reset(0);
			//hal_dac_link_layer_test(link_layer_test_id);
		}

		if (prbs_test_enable) {
			prbs_test_enable = FALSE;
			hal_dac_prbs_test(0, 1);
			hal_dac_prbs_test(4, 1);
		}
	}
}

//----------------------------------------------------------------------------
// Function Name		: hal_dac_link_layer_test()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_dac_link_layer_test(u16 link_layer_test_id) {

	u16 reg;
	u16 alarm_lane[DAC_LANE_COUNT], alarm_common, alarm_short_los;
	u16 error_count_link[DAC_LINK_COUNT];
	u8	loop = TRUE;

	// To run the PRBS test on the DAC, users first need to setup the DAC for normal use,
	// then make the following SPI writes:
	//
	// 1. config74, set bits 4:0 to 0x1E to disable JESD clock.
	// 2. config61, set bits 14:12 to 0x2 to enable the 7-bit PRBS test pattern; or set bits 14:12 to 0x3 to enable the
	// 	  23-bit PRBS test pattern; or set bits 14:12 to 0x4 to enable the 31-bit PRBS test pattern.
	// 3. config27, set bits 11:8 to 0x3 to output PRBS test fail on ALARM terminal.
	// 4. config27, set bits 14:12 to the lane to be tested (0 through 7).
	// 5. config62, make sure bits 12:11 are set to 0x0 to disable character alignment.
	//
	// Users should monitor the ALARM terminal to see the results of the test. If the test is failing, ALARM will be high
	// (or toggling if marginal). If the test is passing, the ALARM will be low.

	if (dac_initialized) {

		// Switch EMIO SPI to DAC SPI
		hal_spi_set_mux(SPI_MUX_DAC);

		// Set JESD_TEST_SEQ[b7:b6]=0-Normal / 1-D21.5 / 2-K28.5 / 3-ILA Sequence
		reg = hal_dac_read_reg(0x4A);
		reg &= 0xFF3F;
		link_layer_test_id &= 0x0003;
		reg |= (link_layer_test_id << 6);
		hal_dac_write_reg(0x4A, reg);

		// Check ALARM signal and read all alarms
		hal_dac_read_alarm(TRUE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
		while (loop) {
			hal_dac_read_alarm(FALSE, alarm_lane, &alarm_common, &alarm_short_los, error_count_link);
		}
	}
}

0 Ebenezer Dwobeng over 8 years ago in reply to TAYLAN ERTAŞ

TI__Genius 9695 points

Hi Taylan,

I tested your exact mode and I have attached the LMK and DAC settings that I used to get the DAC working. I was not able to test the config file you attached in your previous post because the format of the file is not compatible with the DACs GUI. Can you compare this configuration with what you have currently?

Thanks,

Eben.400MSPS_LMF_4421_external_clk.cfg

0 TAYLAN ERTAŞ over 8 years ago in reply to Ebenezer Dwobeng

Prodigy 100 points

Hi Ebenezer,

We finally figured out the problem. It is independent from the configuration. In our hardware, there was a violation of the voltage levels for SYSREF signal. The output type was LVPECL_1600/2000. In EVM hardware, there is a voltage divider at the output of LMK04828 and the output type configuration is set to LCPECL. We updated our hardware like EVM so it is working successfully now and we observe meaningful voltage levels at the DAC outputs.

But i have another problem now. May be, this can be issued in xilinx forum. I think, my problem is related with the AXI4 streaming interface and the mapping in FPGA code before JESD204 IP core. We generate ramp signal and send it to only one DAC output (for example DAC-A output). Data for other DAC outputs is zero.

For LMFS=4421 HighDensity=0, data will be sent in each lane as below (refering to DAC37J84 datasheet)

Lane-0: DA0[15:8] DA0[7:0] DA1[15:8] DA1[7:0] (DA0[15:8] will be transfered first, i think)

Lane-1: DB0[15:8] DB0[7:0] DB1[15:8] DB1[7:0]

Lane-2: DC0[15:8] DC0[7:0] DC1[15:8] DC1[7:0]

Lane-3: DD0[15:8] DD0[7:0] DD1[15:8] DD1[7:0]

Refering to the section "Interfacing to the AXI-4 Stream Data Interface" and "Transport Layer Mapping" of Xilinx JESD204 IP_v6.1 (Vivado.2015.2) document, the 128-bit axi stream data to the JESD IP core should be as below:

tx_tdata[31:0] = DA1[7:0] & DA1[15:8] & DA0[7:0] & DA0[15:8]; for lane-0 / DAC-A
tx_tdata[63:32] = DB1[7:0] & DB1[15:8] & DB0[7:0] & DB0[15:8]; for lane-1 / DAC-B

tx_tdata[95:64] = DC1[7:0] & DC1[15:8] & DC0[7:0] & DC0[15:8]; for lane-2 / DAC-C

tx_tdata[127:96] = DD1[7:0] & DD1[15:8] & DD0[7:0] & DD0[15:8]; for lane-3 / DAC-D

With this mapping, we get a ramp signal shown in the attachment. Ramp signal repeats itself every 256 sample. Somehow, DAC always gets 2nd/4th/6th... samples as zero.
What is the mistake with my settings or mapping?

And also i don't check "tx_start_of_frame" & "tx_start_of_multiframe" signals coming from JESD IP core for now.

Note: I also attached the updated DAC configuration of my hardware. You need some modifications to use it in EVM.

Thanks for your support.
Best regards.

400MSPS_LMF_4421_external_clk_TE.cfg

0 TAYLAN ERTAŞ over 8 years ago in reply to TAYLAN ERTAŞ

Prodigy 100 points

Ebenezer,

Forvet the problem in the previous post. I’ve fixed all right now and it works successfully. It seems that my comments on AXI stream data are all correct.

Again thanks for your supports.
Best regards.

0 Ebenezer Dwobeng over 8 years ago in reply to TAYLAN ERTAŞ

TI__Genius 9695 points

Hi Taylan,

Thanks for the update.

Eben.

Data converters

Data converters forum

DAC37J84: DAC37J84