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DAC104S085: Need Clarification About the Timing Requirement for SPI Interface on DAC104S085

mina magdy
Prodigy 10 points

Part Number: DAC104S085

Hello,

Regarding to the Timing Requirement for SPI Interface on DAC104S085, The Timing for MIN is Greater than the Timing for the TYP which is not clear for me.

ex: for the SCLK Cycle Time Minimum Value should be 33 us and Typically it should be 25 us, Also it stated that T_actual Should be more than T_minimum and now T_typical is less than T_minimum.

also regarding given SPI Serial Timing Diagram

should we Enable the Sclk two Cycle Before de-asserting the ChipSelect(SYNC_n) or it is not required and the given waveform is OK.

  • 0
    TI__Guru 56933 points
    Hi Mina,

    The 25ns is the typical specification at room temperature only. The 33ns is minimum for guaranteed operation across the temperature range (-40 to 125°C). If your application is expected to work in extreme temperature environments, then you should should operate the clock at a slower speed. If you expect the device to be near room, then you can operate at faster speeds.

    Your SPI frame should be okay. The diagram is just showing what it could look like if you had a continuous SPI clock.

    Thanks!
    Paul