ADC12DJ3200: JMODE0, Cannot linked

user5148757

Part Number: ADC12DJ3200

Dear:

I am using the ADC12DJ3200, it works at the JMODE0,12-bit, Single Channel, 8 lanes. The clk_in = 2.4G, use the INA. I use a FPGA,connected the ADC through 204b,but I failed to get the 204b connected.

Can you give me a .cfg as reference to set the ADC?

Thank you .

Best Wish.

xuan.

over 7 years ago

0 Jalen Tate89 over 7 years ago

TI__Genius 9675 points

We are looking into your question.

Jalen

0 Jim Brinkhurst1 over 7 years ago in reply to Jalen Tate89

TI__Mastermind 44680 points

Hi user
Are you using the ADC12DJ3200EVM, or a board of your own design?
Similarly, are you using an off-the-shelf FPGA board from Xilinx or Intel/Altera, or is the FPGA capture solution your own design?
In any case please provide more details about the FPGA solution being used, and how the ADC12DJ3200 is connected to the FPGA. If this is a board of your own design, please provide a schematic showing the ADC to FPGA connections.
Best regards,
Jim B

0 user5148757 over 7 years ago in reply to Jim Brinkhurst1

Prodigy 140 points

dear:

I use my own FPGA board，I just want a file of .cfg as reference ,thanks

best wishes

xuan

0 Jim Brinkhurst1 over 7 years ago in reply to user5148757

TI__Mastermind 44680 points

Hi user

If you have the ADC12DJxx00 EVM GUI installed you can find the configuration files for each JMODE in the following folder location:

C:\Program Files (x86)\Texas Instruments\ADC12DJxx00 GUI\Configuration Files

For convenience I have attached the JMODE0 file here:

/cfs-file/__key/communityserver-discussions-components-files/73/0830.ADC12DJxx00_5F00_JMODE0.cfg

This file sets the ADC into JMODE0 with foreground calibration mode. The SYSREF receiver and SYSREF processing are disabled. This is the simplest setup to use for initial JESD204B link bring-up. Once you have the link operating you can start to add configuration changes if needed.

Best regards,

Jim B

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ADC12DJ3200: JMODE0, Cannot linked