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DAC5681Z: Questions on clock rates

Part Number: DAC5681Z
Other Parts Discussed in Thread: DAC5682Z, DAC5681, DAC3482
Hi,

1. 
When using the DAC5681Z we don’t want to use it to the maximum ratings, only to 125 Mhz (CLKIN/C). PLL = bypass and no interpolation.
Important for the use case is the exact sample synchronization of multiple channels (more channels than exist in a 1/2/4 x DAC).
According to chapter "7.3.16.2 Recommended Multi-Dac Synchronization Procedure" the synchronization accuracy is limited to "... the outputs of all DACs will be synchronized to within ±1 DAC clock cycle.".
This is logic through the data fifo with the two clocks DCLKP/N (input) and CLKIN/C (output).
The question is if there exists an area of the phase position between these two clock signals where the SYNCP/N switchover (and potentially further internal signals) works without tSetup/tHold time violations and therefor is identical in all chips?
What would be the times?

2.
If possible there is an optional 2x or 4x interpolation with PLL planned (but still 125Mhz CLKIN/C frequency). The phase position will obviously be a different one. Is the reference (and therefore the window where the SYNCP/N edges may occur) still the low CLKIN/C clock rate or the internal faster clock rate (250 / 500 MHz)? So does the area where SYNC edge occurs get less?
I haven’t found this information in the data sheet. Also in the "Figure 42. Clock and Data Timing Diagram" this is not shown.

Thanks
Fred
  • Hi Frederik,

    It am having trouble understanding your question. Can you please explain to me what you exactly want?

    Regards,
    Neeraj Gill
  • Hi GIll,

    let me repost and try to get the format right. Is it still unclear? Then I would ask the customer to comment directly.

    1.
    When using the DAC5681Z we don’t want to use it to the maximum ratings, only to 125 Mhz (CLKIN/C). PLL = bypass and no interpolation. Important for the use case is the exact sample synchronization of multiple channels (more channels than exist in a 1/2/4 x DAC). According to chapter "7.3.16.2 Recommended Multi-Dac Synchronization Procedure" the synchronization accuracy is limited to "... the outputs of all DACs will be synchronized to within ±1 DAC clock cycle.". This is logic through the data fifo with the two clocks DCLKP/N (input) and CLKIN/C (output). The question is if there exists an area of the phase position between these two clock signals where the SYNCP/N switchover (and potentially further internal signals) works without tSetup/tHold time violations and therefor is identical in all chips? What would be the times?

    2.
    If possible there is an optional 2x or 4x interpolation with PLL planned (but still 125Mhz CLKIN/C frequency). The phase position will obviously be a different one. Is the reference (and therefore the window where the SYNCP/N edges may occur) still the low CLKIN/C clock rate or the internal faster clock rate (250 / 500 MHz)? So does the area where SYNC edge occurs get less? I haven’t found this information in the data sheet. Also in the "Figure 42. Clock and Data Timing Diagram" this is not shown.

    Thanks
    Fred
  • Hi Gill, hi Fred,

    I am one of the developers on this project.

    So we do have two major scenarios/use cases that we would like to cope:

    1) No Interpolation: 1:1 Data rate to DAC-Rate, Input Data Clk up to 125 MHz which can be a input data rate up to 250 MSps.

    We need to have multiple DAC channels and these must have completely aligned samples at their outputs, so hence the identical pipeline length through the DAC is required. This requirement obviously cannot be met when using the built-in FIFO with the "single synchronization" method described in the data sheet of the DAC5681, DAC5681z or DAC5682z. Because the +/-1 Sample would not be enough for us.

    We do however generate the Clk to the DAC (CLKIN) froma clock generation circuit that also feeds the FPGA supplying the data and data clock to the DCLK port of the DAC. So the question is, do we stand a chance to not-use the built-in FIFO and still, by properly adjusting the phase relation between  DCLK and CLKIN to not generate any internal setup/hold violations when crossing from the DCLK domain to the CLKIN domain and if possible, what are the time relations required ?

    2)  Optional x2 or x4 Interpolation: 1:2 and 1:4 data rate to DAC-Rate, same input rate as above, but internal multiplication by built-in PLL

    In this case, the secondary clock domain is no longer directly supplied by the CLKIN pin, but is coming from the PLL (multiplied by 2 or 4).

    Would the above setup/hold timings still apply, when the DAC clock is now generated by the PLL or in other words what phase shift does the PLL add to the DAC clock ? And more important, would it still be possible to reliably transfer from DCLK domain to DACCLK domain ?

    If any more information is required please let me know.

    Best regards

    Bjoern

  • Hi Bjoern,

    There is no easy way to meet your requirement bypassing the FIFO and meeting the setup/hold timing when crossing from the DCLK domain to the CLKIN domain.
    Given your use case I would recommend using DAC3482 device which has FRAME CLK and OSTRP clock signals to synchronize across the two clock domains.

    Regards,
    Neeraj
  • Hi Neeraj,

    thanks a lot for your answer on that matter.

    The DAC3482 is unfortunately not of real interest to us, as it incorporates an even more complicated synchronization procedure with more required signals from the FPGA (although admittedly then allowing sample exact synchronization of multiple devices), but it does lack many of the desired features from the DAC5681 such as:

    - no one channel version available

    - inconvenient clock common mode level of 0.2 V ... which is hard to do with our requirements of using a DC coupled clock

    - requirement of an additional and rather unconventional 1.2V power rail

    - no nice factor ten (2..20mA) output current range

    - no double speed (DDR input to just one channel) clocking without interpolation

    - no nice easy to use QFN package

    Thanks again and best regards

    Bjoern