Other Parts Discussed in Thread: DAC5682Z, DAC5681, DAC3482
Hi,
1.
When using the DAC5681Z we don’t want to use it to the maximum ratings, only to 125 Mhz (CLKIN/C). PLL = bypass and no interpolation.
Important for the use case is the exact sample synchronization of multiple channels (more channels than exist in a 1/2/4 x DAC).
According to chapter "7.3.16.2 Recommended Multi-Dac Synchronization Procedure" the synchronization accuracy is limited to "... the outputs of all DACs will be synchronized to within ±1 DAC clock cycle.".
This is logic through the data fifo with the two clocks DCLKP/N (input) and CLKIN/C (output).
The question is if there exists an area of the phase position between these two clock signals where the SYNCP/N switchover (and potentially further internal signals) works without tSetup/tHold time violations and therefor is identical in all chips?
What would be the times?
2.
If possible there is an optional 2x or 4x interpolation with PLL planned (but still 125Mhz CLKIN/C frequency). The phase position will obviously be a different one. Is the reference (and therefore the window where the SYNCP/N edges may occur) still the low CLKIN/C clock rate or the internal faster clock rate (250 / 500 MHz)? So does the area where SYNC edge occurs get less?
I haven’t found this information in the data sheet. Also in the "Figure 42. Clock and Data Timing Diagram" this is not shown.
Thanks
Fred