DAC output distorted with different PRF pulses

Madan,

We are looking into this.

Regards,

Jim

Hi Madan,

can you please tell me what status are reading for DLL lock when you are seeing distortion in your output signal. Can you enable sw_sync_SEL by setting config3 bit 0 to 1 and then asserting the SW_SYNC(bit 1 the value of 1) and see if you output signal is improved.

Regards,

Neeraj

Hi ,

Firstly I cannot use software sync because I cannot keep programming SW_sync bit at the start of every pulse as a transmit enable control as it affects my switching time. therefore i am using Hardware SYNC.

secondly, if at all I use SW sync by setting config3= 0x73 or 0x 72 or 0x70 , i am getting some other random dac output

Regards

Madan

Hi Madan,

Can you please send me the pattern file you are using in CSV form so that I can try it on my evm and see I am seeing any issues with it.

Regards,
Neeraj

hi,

this is the samples file(.xlsx) for a LFM of carrier 60Mhz,

bandwidth 5Mhz and pulsewidth 13.68 us at a Sample rate of 250Msps

Untitled 1.xlsx

Regards,

Madan

Team,
Please guide to resolve the issue.

Hi Madan,

Can you please try to program DAC5681z's registers to following values and see if it helps with the distortion.

Can you please make the number samples in the file that you send me multiple of 32. Hsdc pro software only accepts # of samples as a multiple of 32.

Regards,

Neeraj

Hi Madan,

I forgot to ask in my previous post. When you are seeing distortion in the output signal, can please read status of DLL_LOCK bit(register 0 bit 6)? If the DLL is lock you should read this as bit 6 at 1.

Regards,

Neeraj