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ADS1278: CLK frequency dependency in FSYNC fromat

Tejas s j
Intellectual 415 points
Part Number: ADS1278

I am using ADS1278 in FSYNC format in Low-Speed mode. I am using ADS1278 in an application where the sampling rate(SR) will vary from 50 to 8000 sps.
I drive the FSYNC pin high every at 1/SR time for 50 clk cycles and drive the pin low.

CLK freq = 22Mhz
SCLK freq = 22Mhz

According to Table.8 in the datasheet, f_data will be 8593.75.

Question:

1. Let's consider the case where the ADC should be operated in 50sps. As the f_clk sets the ADC sampling rate to 8593.75 and the effective sampling rate is decided by FSYNC pin, Will the effective sampling rate be scaled down from 8593.75 to 50?
2. What is the effect of a higher f_clk, when the sampling rate wanted is lower than that?
3. Is my approach to achieving different sampling rates by keeping f_clk constant and driving the FSYNC pin based on SR requirement correct?

Thank you,

Tejas 

  • 0
    TI__Guru 66206 points

    Hello Tejas,

    Thank you for your post and welcome to our forum!

    CLK = 22 MHz will produce an output data rate of 8593.75 SPS in Low-Speed Mode. The only way to scale the output data rate down to 50 SPS in the same mode is to reduce the CLK input frequency to 128 kHz.

    The FSYNC interface signal must be continuous and exactly equal to the output data rate. In Low-Speed Mode with CLKDIV = 1, there must be exactly 2,560 CLK periods in each frame. The duty cycle of FSYNC can be nearly anything with a minimum pulse width (high or low) of 1 SCLK period.

    Best Regards,