ADC12DJ3200: clock leakage using Nyquist zone 3

Hi Tom

This ADC is architected using 2-way interleaving for ADC-A and 2-way interleaving for ADC-B. When operating in dual input modes there will be some interleaving spur energy at Fs/2 due to offset mismatch between the 2 converters, and energy at Fs/2-Fin due to gain and/or timing mismatch between the 2 converters.

When used in the single input modes all 4 converters are interleaved. In this configuration offset spurs will be present at Fs/4 and Fs/2. Gain and timing spurs will be present at Fs/2-Fin, Fs/4+Fin and Fs/4-Fin.

The ADC is factory trimmed with 3200 MHz clock frequency to minimize timing related spurs. Unfortunately using the device with a lower frequency clock can result in increased Fs/2-Fin levels as the timing trim needed is dependent on clock frequency. It is possible to re-optimize the interleave timing trim setting at the lower clock frequency. Once the new optimal value is determined it will need to be programmed for that ADC device each time it is powered up.

This earlier E2E post has the details for adjusting the timing trim setting:

https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/664636/2445075

If this doesn't address the clock leakage you are seeing please provide more details on the specific spur frequencies you are seeing for specific Fclk, Fin and JMODE settings.

Best regards,

Jim B