DDC1128EVM: output data from the EVM

Shinichi Inoue

Guru 19671 points

Part Number: DDC1128EVM
Other Parts Discussed in Thread: DDC1128

Dear Specialists,

My customer is testing DDC11C128EVM and has inqries.

I would be grateful if you could advise.

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We are proceeding with verification on the evaluation board of DDC 1128, but I do not know the details of the data from the software attached to that board.

Now it is a situation that I am in trouble judging whether evaluation results are appropriate.

I would like to confirm about this.

In the state of setting (DDC1128 EVM_Setting.jpg) as shown in the attached figure, data is acquired by Save data memory.
At this time, when acquiring data when setting the value of Bit 8 of the configuration register of the DDC 1128 to 0,
Is it correct to set the FPGA to 16 bits too?

If it is set to 16 bits, the obtained data seems to exceed 16000000.
It seems that it is output with 24 bit data, but I do not know in what frmat the number is being output.
It is EVM data, please refer to attached data.
DDC 1128 16 bit output setting, FPGA also 16 bit setting.

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I appreciate your great help in advance.

Best regards,

Shinichi

with AIB_0R1VINPUT_700μsec_Range0_16bit.txt

over 5 years ago

0 Matt Mendez over 5 years ago

TI__Intellectual 2885 points

Hello Shinichi,

Please email me at mendez@ti.com. We can discuss this offline. Thank you

0 Shinichi Inoue over 5 years ago in reply to Matt Mendez

Guru 19671 points

Hi Matt,

Thank you for your reply.

I sent the email to you.

Could you please advise?

I appreciate your great help.

Best regards,

Shinichi

0 Shinichi Inoue over 5 years ago in reply to Shinichi Inoue

Guru 19671 points

Hi Matt,

This is just a reminder that I’m waiting for your email reply.

I sent your email address a few days ago.

Best regards,
Shinichi

0 Matt Mendez over 5 years ago in reply to Shinichi Inoue

TI__Intellectual 2885 points

Hi Shinichi,

You are correct in setting bit 8 to 0 to set the output to be in 16-bit. You also need to change the format in the GUI on the left side, there is an entry labeled "Format" and it is set to 20bit by default. Please try changing this to 16bit. Thanks

0 Shinichi Inoue over 5 years ago in reply to Matt Mendez

Guru 19671 points

Hi Matt,

Thank you for your reply.

I' d like to confirm again.

I'd be grateful if you could advise.

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When DDC 1128 is set to 16 bit output and FPGA is also set to 16 bit , the obtained data seems to be 24 bits, because of exceeding 160000.

The attached file before shows that condition.

Is this data FPGA specification?

Is 16 bits effective and necessary to subtract 8 bits?

Or another format, in this case , could you please tell me what to do?

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I would appreciate receiving your feedback as soon as possible.

I am looking forward to hearing from you.

Best regards,

Shinichi

0 Shinichi Inoue over 5 years ago in reply to Shinichi Inoue

Guru 19671 points

Hi Matt,

The customer are in a big hurry for the issue below.
Your immediate response is highly appreciated.

Best regards,

Shinichi

0 Matt Mendez over 5 years ago in reply to Shinichi Inoue

TI__Intellectual 2885 points

Going to email you answer now. sorry for long wait.

0 Shinichi Inoue over 5 years ago in reply to Matt Mendez

Guru 19671 points

Hi Matt,

Thank you for your reply.

I confirmed your email.

I could understand the meaning of the output data.

I appreciate your great help and cooperation.

Best regards,

Shinichi

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DDC1128EVM: output data from the EVM