Other Parts Discussed in Thread: ADC12J4000,
Hello!
We are supposed to work with a combo ADC12J4000 + Xilinx VC707 (Virtex 7 FPGA). We haven't received the ADC kit yet but, since our timetable for the project is quite pressing, we would be happy to have an example of how to configure the ADC and LMK registers so that we could use the kit in the following configurations:
1. 4Gsps raw ADC stream;
2. DDC with decimation factor 4 (1Gsps Re+Im).
Thank you in advance,
Kind regards,
Ilya.