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Original question:

ADS1220: Power-up ramp timing question

ADS1220: Power-Supply ramp rate

Masanori Tachibana
Genius 5350 points
Part Number:

Hi support team,

The following description is added in Rev. C of the data sheet.
Section "10.2 Power-Supply Ramp Rate" on page 60

In this regard, I read the following E2E article.
"ADS1220: Power-up ramp timing question"
e2e.ti.com/.../648362

Now, I have some questions about the ADS1120.

[Question]
1. If the power-supply ramp rate do not satisfy the conditions described in 10.2, such as the power supply raises earlier than 1 V per 50 μs, I think ADS1120 may not start up.
Is my understanding correct?

2. I understand that there is no restriction on the power-supply ramp rate when supplying clock externally.
If the power-supply ramp rate do not satisfy, I think here is a possibility that the internal clock may not start up.
Is my understanding correct?

3. Do the devices shipped before revising the data sheet also require the power-supply ramp condition?
(Does the ADS1120 have no revision and do all the devices subject to this restriction?)

Sincerely,
M. Tachibana

  • 0
    TI__Guru** 113765 points

    Hi Tachibana-san,

    See my responses below.

    Best regards,

    Bob B

    Masanori Tachibana said:

    Part Number: ADS1120

    Hi support team,

    The following description is added in Rev. C of the data sheet.
    Section "10.2 Power-Supply Ramp Rate" on page 60

    In this regard, I read the following E2E article.
    "ADS1220: Power-up ramp timing question"
    e2e.ti.com/.../648362

    Now, I have some questions about the ADS1120.

    [Question]
    1. If the power-supply ramp rate do not satisfy the conditions described in 10.2, such as the power supply raises earlier than 1 V per 50 μs, I think ADS1120 may not start up.
    Is my understanding correct? [Bob B] Yes, the ADS1120 has the same requirement as the ADS1220.  The most critical range is from 0 to about 1.8V and we have found that about 10 to 20% of devices will not start as expected with very fast startup ramps (10ns/V as an example). The supply ramp requirement covers the entire temperature operating range of the ADS1120 (or ADS1220).  Using the suggested supply ramp will allow for correct startup over all supply voltages and operating temperatures specified as recommended operating conditions for the device.  This ramp rate is for the supplies at the ADS1120 device pins.  This may be different than the ramp rate at the supply source due to trace inductance and capacitance connected to the supplies. In most cases the impedance of the traces allow sufficient slowing of the supply source ramp at the device supply pins in the critical startup region.

    2. I understand that there is no restriction on the power-supply ramp rate when supplying clock externally.
    If the power-supply ramp rate do not satisfy, I think here is a possibility that the internal clock may not start up.
    Is my understanding correct? [Bob B] What actually happens is the oscillator starts and then shuts down due to an incomplete power-on reset (POR). Internally the device then switches to the external clock input and blocks communication due to an incomplete POR.  Sending a RESET command will properly reset the device, but because the ADS1120 has not started properly all communication is locked out from the device.  Using the external clock will complete the POR process after 32 clocks are sent.  So it is possible to use a fast supply ramp by using the external clock as either continuous clock or by just sending 32 clocks and then sending the RESET command. 

    3. Do the devices shipped before revising the data sheet also require the power-supply ramp condition? [Bob B] Yes as there has been no silicon changes since the devices were released.
    (Does the ADS1120 have no revision and do all the devices subject to this restriction?) [Bob B] To ensure that all devices using the internal oscillator start as expected the suggested supply ramp should be used.  As I stated earlier, what we have seen is the startup issue is device and lot dependent and affects statistically about 10 to 20% of devices. We have only seen this as a customer issue in 3 cases known to us.  As this is a very popular device with many thousands of units shipped we have seen very few issues relative to the number of devices shipped.  The ramp rate addition to the datasheet was requested by the customer that first discovered the issue where the ramp rate was approximately 10 to 20ns/V (which is unusually fast).

    Sincerely,
    M. Tachibana

  • 0 in reply to Bob Benjamin
    Genius 5350 points

    Hi Bob-san,

    Thank you for teaching me in detailed.
    I understood very well regarding the problem in case the power-supply ramp rate is faster than 1 V per 50 μs.

    By the way, I think this problem will not be progressive.
    For example, if the customer use normal devices for a long time, I think this problem will not occur or get not worse.
    My recognition is correct, isn't it?

    Sincerely,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    TI__Guru** 113765 points
    Hi Tachibana-san,

    If a customer has had a working system for quite some time and they have not seen any issues in the past, then most likely they never will see an issue. However there is not a guarantee as there is some lot to lot dependencies. I would suggest any new designs use the suggested ramp rate.

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Genius 5350 points
    Hi Bob-san,

    I got relieved with your explanation.
    Your advice is very helpful.
    We will recommend with the customer to apply slower power-supply ramp rate for the new design.

    Sincerely,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    Genius 5350 points
    Hi Bob-san,

    I have additional questions regarding ADS1120.
    1. Is it possible to perform SPI communication when the power-supply ramp rises fast and the internal clock is stopped?
    How does the IC behave if SPI communication accesses from the outside when the internal clock is stopped?

    2. I would like you to confirm wheather the power-on waveform of the customer is no problem or not.
    I want to send the measured waveform to your private address, so could you tell me the address?

    Sincerely,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    TI__Guru** 113765 points

    Hi Tachibana-san,

    See my comments below.

    Best regards,

    Bob B

    Masanori Tachibana said:
    Hi Bob-san,

    I have additional questions regarding ADS1120.
    1. Is it possible to perform SPI communication when the power-supply ramp rises fast and the internal clock is stopped? [Bob] No, for ADS1220 and ADS1120 devices if the fast ramp stops and blocks the internal clock the power-on reset (POR) does not complete. Because POR has not completed, logic prevents communication through SPI.  As the device cannot properly receive commands, the RESET command will have no effect.
    How does the IC behave if SPI communication accesses from the outside when the internal clock is stopped? [Bob] The device will be in a low power state and idle.  It cannot accept any SPI commands until the internal logic has unlocked the SPI communication.  The fast supply ramp on DVDD may cause some devices to incorrectly place the external clock pin as the clocking source for the device.  The internal logic to the device is now expecting external clocking and shuts down the internal oscillator to lower power consumption.  As this happens very early in the power-up process, the POR does not complete due to an insufficient number of clocks to complete the process.  If an external clock is provided there will never be an issue and the POR ramp is of no concern.  If the internal clock is used, then the ramp must be followed so that all devices start properly over all operating temperatures.  If the ramp rate cannot be followed, then it is suggested that the external CLK pin be connected to a GPIO. If the device stalls due to the internal clock stoppage, a minimum of 32 clock pulses on the CLK pin will release the SPI communication and the RESET command can then be issued through SPI communication. One way of determining that the device has not started correctly is DRDY remains high and never goes low.  The operating state of the device is to complete POR, take one conversion and then go to idle.  After about 51ms after power-up, the DRDY pin should go low.  If it does not, then there is an issue.  Another method is to attempt to read the registers approximately 50us after power-up.  If the registers are not the default values, then there is an issue.  Once the issue is determined, send 32 clock pulses (222ns period of longer) to the device CLK pin.  32 clocks completes the POR startup and unlocks the SPI communication.  Send the RESET command to return to the internal oscillator.

    2. I would like you to confirm wheather the power-on waveform of the customer is no problem or not.
    I want to send the measured waveform to your private address, so could you tell me the address? [Bob B] If the DVDD supply power-up follows the suggested ramp rate shown in the datasheet there will not be an issue.  A modified ramp rate may be considered with the critical time from 0V to approximately 1.8V.  I can review the ramp rate, but this must be observed directly at the DVDD pin of the device and not at the power source.  As the startup issue is lot and device dependent, what may work for some devices may not work for others.  The issue affects about 10 to 20% of devices and the only way to be certain is to follow the ramp rate shown in the datasheet.  I can be reached through email at pa_deltasigma_apps@ti.com



    Sincerely,
    M. Tachibana

  • 0 in reply to Bob Benjamin
    Genius 5350 points

    Hi Bob-san,

    Thank you for kindly teaching me.
    I understood that SPI communication is impossible when the internal clock is stopped (when being incompleted POR).

    I have sent the waveform data of power supply ramp to the e-mail address you taught me.

    Sincerely,
    M. Tachibana