This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS54J60: Fast Overrange Indication

Part Number: ADS54J60

Dear E2E Masters,

We use high speed ADS5454J60 for data capturing and post analysis.

As described in the datasheet, the ADC provides FOVR indication in case the input voltage exceeds programmable threshold.

The datasheet specify that FOVR is presented after 18 clock cycles + tPD (~4ns).

In addition, the FOVR can either (1) replace the sample LSB or (2) override the PDN/SDOUT pins (if configured).

QW1) Considering the 18-clock cycles latency. Is it defined from sampling clock to discrete IO indication? If so, what is the latency when the FOVR is embedded in the downstream data?  

QW2) In case FOVR replace the LSB, is there any time-correlation between this sample and the FOVR? i.e. this sample is corrupted and should be ignored?

Thanks,

  • Nissan,

    For #1, the delay is 62 CLK cycles.

    For #2, In this mode, every data word that has the LSB high, is considered out of range data and corrupted. Every occurrence will get tagged.

    Regards,

    Jim

  • Hi Jim,

     

    Thank you for your answer.

    If I correctly understand, using the embedded LSB method would results in 15-bit resolution, effectively.

    Do you have additional information if and how much the ENOB would degrade in this method? Assume 410MHz clock for sampling.

     

    BR,

    Nissan