Dear E2E Masters,
We use high speed ADS5454J60 for data capturing and post analysis.
As described in the datasheet, the ADC provides FOVR indication in case the input voltage exceeds programmable threshold.
The datasheet specify that FOVR is presented after 18 clock cycles + tPD (~4ns).
In addition, the FOVR can either (1) replace the sample LSB or (2) override the PDN/SDOUT pins (if configured).
QW1) Considering the 18-clock cycles latency. Is it defined from sampling clock to discrete IO indication? If so, what is the latency when the FOVR is embedded in the downstream data?
QW2) In case FOVR replace the LSB, is there any time-correlation between this sample and the FOVR? i.e. this sample is corrupted and should be ignored?
Thanks,