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AMC7836: The effect of the reset pin

Lacey Lin
Intellectual 2900 points
Part Number: AMC7836

Hi team,

If we put the reset pin of AMC7836 to GND all the time, can we use the SPI to read back the register?

Also can we use the SPI to write the register or does the register value keep the default value all the time when the reset pin is low?

Please help to answer above questions.

Lacey

Thanks a lot!

  • 0
    TI__Mastermind 46290 points
    Lacey,

    The !RESET pin is an active low input, after 20ns minimum low time the device is held in the reset state. While in the reset state and up to 250us after !RESET is released, communication with the device is invalid per the datasheet.

    Can you explain more about what is actually trying to be achieved in this situation?
  • 0 in reply to Kevin Duke
    TI__Intellectual 2900 points
    Hi Kevin,
    Thanks for your reply!
    So you mean in the reset state, the communication is invalid.
    it means we can't access the register while the chip is in the reset state.
    is it right?
    Another question is if we just put the reset pin to low, not release the pin, can we reset the register value to the default value. That's the if the reset is due to the falling edge, rising edge or the low level sampling?

    For the detail, I need to check with customer in next Monday!

    Lacey
    Thanks a lot!
  • 0 in reply to Lacey Lin
    TI__Guru 53773 points
    Hi Lacey,

    While the device is in reset (reset is asserted low) the device will not have valid communication. When the reset is released, all registers will be set to the default values.

    Thanks!
    Paul
  • 0 in reply to Paul_Frost
    TI__Intellectual 2900 points
    Hi Paul,
    My customer need to do software alarm when the reset pin is short to ground.
    So they want to know if they do the normal operation like write register 0x0F to 0x10, and then read the value of register 0x20-0x49 in the reset status( the reset pin is always low). What's the value of the 0x20-0x49.
    Will the value in register 0x20 to 0x49 be 0x00 or 0xFF.
    They want to identify if the reset pin is ground according to the value read back in 0x20 to 0x49.

    Lacey
    Thanks a lot!
  • 0 in reply to Lacey Lin
    TI__Guru 53773 points
    Hi Lacey,

    I understand. I just measured this on the EVM and it seems the device responds with 0xFF to all read commands when the RESET pin is low.

    Thanks!
    Paul
  • 0 in reply to Paul_Frost
    TI__Guru 53773 points
    Hi Lacey,

    One more note, it is possible for the SDO pin to be High-Z during the reset process. I recommend that they add a ~50kΩ pull-up resistor to SDO if they are going to being reading from the device round a reset event.

    Thanks!
    Paul
  • 0 in reply to Paul_Frost
    TI__Intellectual 2900 points
    Hi Paul,
    Thanks so much for your help!
    it's very helpful for my customer.

    Lacey
  • 0 in reply to Lacey Lin
    TI__Intellectual 2900 points
    Hi Paul,
    Customer also do the test in their production board.
    And they find when there is a pull-up resistor, the value read during the reset status is always FF.
    But when there is no pull-up resistor, some chip will read out 0.
    Please help to answer below question:
    1.In their previous application, they don't add the pull-up resistor, so they want us to evaluate if they add the pull-up resistor in the SDO in the current schematic, will this affect the communication when the chip work normally?

    2. In addition, they also want to know if the time between the write and read register will affect the value read out when the chip is in the reset status?

    Lacey
    Thanks a lot!
  • 0 in reply to Lacey Lin
    TI__Guru 53773 points
    Hi Lacey,

    I was able to confirm with the design team that the SDO pin is High-Z the entire time it is reset. The SDM-USB-DIG (used on the EVM) has a internal pull up, which is why I always read 0xFF as a response. A pull up/pull down should be present in their application if they are going to read the device in reset. We specify a low level output voltage of IOVDD-.4V when the IO pin is sinking 1mA. I would make the pullup a large enough value not to compromise the VIH requirements of the MCU they are using. I recommend a value >=10kΩ, which should not affect the communication.

    There are no requirements on the timing during the reset state as the device will not latch any data or respond.

    Thanks!
    Paul