I am using this device at 2 GSPS in Interleave mode.
When there is no analog input(only noise floor), and repeatedly accumulates at 100us cycle, 500MHz cyclic noise is generated with 100 times accumulate.
The amplitude of cyclic noise fluctuates slightly when calibration is executed.
Initially I thought that the 500 MHz operating clock on the digital circuit side was affected.
However, even if the analog / digital power supply of the ADC device is completely cut off and the analog power supply is supplied by another power supply device, it is generated.
Even if OV is changed and LVDS Vp-p is changed to 510mVp-p, the amplitude of this noise does not attenuate.
Therefore, now I think that it is not the influence of the digital circuit.
I have 2 questions:
- Is there a possibility of 500 MHz periodic noise due to the internal structure of the ADC08D1020?
In the case of Interleave mode, we thought that 1 GHz cyclic noise could be seen. I can not understand why it is 500 MHz cyclic noise.
- amplitude of 24 with accumulate of 100 times, amplitude of 49 with accumulate of 1000 times, is this reasonable for the performance of this device?