Hello Guys,
I have similar problem as you had, and you forgot to post the solution. What was the issue in your case?
According to the datasheet, the CLR pin is falling edge sensitive, so keeping it high or low has no difference in operation.
Andras
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Hello Guys,
I have similar problem as you had, and you forgot to post the solution. What was the issue in your case?
According to the datasheet, the CLR pin is falling edge sensitive, so keeping it high or low has no difference in operation.
Andras
Hello,
My problem is solved today. I make a software reset to the DAC, and increased the delays between the last CLK signal and the SYNC signal. I am not really sure which modification solved the problem... If the software reset is necessary, or the device needs any initialization before usage, it would be nice to included these in the datasheet. I am happy with the default settings of the device, so initially I didn't do any initialization or reset, after power on (with a delay of around 500ms) I started sending the output values through SPI. I also modified the connection of my CLR pin, and now it is connected to VCC.
Regards,
Andras