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ADS131E08: problem with reading the data from ADC!

javad nabavi
Prodigy 90 points

Part Number: ADS131E08

hi,

I designed the Data Acquisition System with ADS131E08 and Sparan 6 FPGA. For handle the ADC, according to the figure 53 in page 50 of datasheet, i wrote VHDL code to reset and configure the ADC.

the ADC's parameters is set to:

fCLK= 2.048 Mhz

fSCLK= 9 Mhz

CONFIG1 = 91 h , CONFIG2 = F0 h , CONFIG3 = C0 h 

CHnSET = 05 h

I wrote the state machine (FSM) by vhdl to configure the ADC:

some of states is used to configure the ADC, in one state send the ID register address to ADC and in the next state received the ID data that is correct. some states send the RDARAC command to ADC Read the captured data, and other states is to control the ADC

For testing the ADC for sampling, i use the resistor division that they are connected to analog inputs.one resistor is connected to 1.2v and another is connected to AGND and center of tow resistor is connected to the INP input and the INN input of ADC is connected to AGND.

when i captured the data, i received the status bits correctly and other bits cna be received that isn't zero.

I test the ADC with code that works correctly but now soddenly the receiving has failed and the ID register data is zero. i guess that driving the analog inputs for sampling is mistake? Right? (i place a 10k resistor in analog inputs that prevent the damage to ADC)

please help me to found the problem and solve it.

regards,

  • 0
    TI__Guru 68966 points

    Hello Javad,

    Thank you for your post and welcome to our forum!

    Would you mind uploading a PDF schematic of your ADS131E08 circuit? This way we can check all the connections to the device.

    The channel settings (CHnSET) cannot be set to 05h. Please use one of the available gain settings listed in Table 17.

    The resistor divider you described (assuming equal resistor values) would only apply 600 mV to the ADC inputs, which will not damage the device. However, since CHnSET[2:0] = 101, you are disconnecting the input voltage from the channels and you are measuring the internal test signal instead. Not a problem, just be aware of the signal you should expect to measure.

    If the device appears unresponsive, try resetting the supplies and issuing a /RESET pulse on pin 36. If the CLK signal is present (I assume you are using the internal clock), the /DRDY pin should toggle at the default data rate after the internal power-on reset is complete.


    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 90 points

    Hello Ryan,

    Thank you for reply.

    My problem solved and it related to Reset Timing. I use the both RESET pin and command for reset the ADC. After resetting the ADC and config the registers, i can able to read the value of registers that was set correctly.

    Now i set the CH1SET register to 11h (pd1 = 0 , Gain1 = 001 and Mux1 = 011) for capture the [0.5 × (AVDD – AVSS)] value that AVDD=3v and AVSS is 0, also Vref= 2.4v.

    The received data is << C0 0F F0 50 0E F6 00 0A 28 00 09 74 00 09 4C 00 0A 0A 00 09 A6 00 09 4C 00 0A 14 >> that the 3 bytes is Status and the next bytes (50 0E F6) is related to the channel 1. According to the datasheet the received data is two's complement format and when i convert it to decimal value and compare it with (AVDD - AVSS)/2, the value is correct.

    thanks for all and best regards,

  • 0 in reply to javad nabavi
    TI__Guru 68966 points
    No problem, Javad. I'm glad you figured it out!

    Regards,