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Dear Sirs,
we have designed an A/D board using 4 ADS1625 interconnected to an FPGA.
We are spotting a really weird behaviour of the ADCs.
Clock is 40MHz as stated in the datasheet, but the dataready output frequency is 5Mhz..
Furthermore the two less significant bits are stuck to zero.
It looks like the ADS1625 (18bit) behave like ADS1605 (16bit).
We have checked the ID on the package and it is the right one ADS1625.
Do you have hints?
Regards,
Michele
Hello Michele,
Thank you for your post and welcome to our forum!
Could you please share the ADS1625 portion of the schematic? I'd like to review all relevant connections to the device. As you would expect, the output data rate for the ADS1625 should always be CLK divided by OSR = 32.
Best Regards,