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ADS7039-Q1: Will SDO output be high impedance when CS is High

Julio Apps
Expert 3665 points
Part Number: ADS7039-Q1

Will SDO output  be high impedance when CS is High. We are looking to use two of these components and tie the two SDO outputs together (with series resistors) and then connect to a digital isolator.

  • 0
    TI__Expert 5575 points

    Hi Julio

    As per ADS7039-Q1 datasheet section 8.3.4, when CS pin is pulled high, ADC data bus is tri-stated.

    Thanks & Regards

    Abhijeet

  • 0 in reply to Abhijeet Godbole
    TI__Expert 4405 points
    Julio,

    As clarified by Abhijeet, “when CS pin is pulled high, ADC data bus is tri-stated”. So if you drive the CS to each device individually, and ensure no overlap, the configuration that you have described will work.

    But looking at this more closely, we have only quoted the min spec for tDZ_CSDO in the datasheet. Ideally a max spec is required to ensure both devices do not drive SDO at the same time. I checked with the designer for this particular device and the max spec for tDZ_CSDO is 20ns.

    Since you are trying to optimize the number of digital isolators used, I guess you will drive a common SCLK to both devices. If you ensure a 1 clock cycle delay (which would be 35ns at the max. SCLK of 28MHz) between the CS fall of one channel to the CS rise of the next, things should work perfectly fine.

    Thanks.

    Regards,
    Sandeep