Dears.
Our Board problem is Serdes PLL does not lock.
I want to know the LOCK of SERDES PLL.
What are the conditions under which the SERDES PLL of the DAC37J82 is unlocked?
Why does "fifo read empty" error appear?
The DAC37J82 is being used with the following Serdes configuration:
LMFS 2221
K=16
Sysref : 9.6Mhz
Fs : 614.4Mhz
interpolation : 4
Lane Rate : 3072Mbps
DAC Clk : 153.6Mhz
External Clock mode.
Complex.
Serdes Lane Rate : 3072Mbps,
Serdes Rate : QuarterRate,
Serdes PLL=3072Mhz,
Serdes Div=1,
Multiply Factor=5,
Serdes RefClk=614.4M
Serdes Lane : LANE 0,LANE 1
DAC_CLK : 614.4Mhz
Interpolation Factor : 4
Thank you.
