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ADS54J66: JESD Link loses lock when signal amplitude > -6dBm

Joseph Mead
Prodigy 80 points
Part Number: ADS54J66
Other Parts Discussed in Thread: , LMK04828

Hi,


I have the ADS54J66 eval board connected to a Xilinx Zynq FPGA and have a strange problem where if I increase the signal amplitude to the ADC above about -6dBm the JESD link appears to lose lock and I start getting bad data.    With smaller input signals everything seems to be working fine.   I am rolling my own JESD receiver core and can successfully see the CGS phase, ILAS phase, and finally data phase.    Attached is the chip scope output from Xilinx which shows a nice sine-wave output when things are working.

I have slowed down the sampling rate to 50Msps, which corresponds to a 1Gbps serial link, so I don't believe this is a signal integrity issue.

When link is working;

When the input signal amplitude is increased above about -6dBm, the link looses lock, many rxcharisk symbols are seen by the GTX receiver as well as rxnotintable errors

If we zoom into the region where it fails, the GTX receiver does a rxbyterealign and rxcommadet, the link receives a K28.5 code (0xBC). see below and then the data gets weird,  after that many rxcharisk symbols are received and rxnotintable errors.   The only way to clear the error is to re-assert the sync pin to start another inititalization.

Thanks for any suggestions.

Joe

  • 0
    TI__Intellectual 2750 points
    Joe,
    We will take a look at this and get back to you.
    Regards,
    Brian
  • 0 in reply to Brian Kincaid
    TI__Guru* 91947 points

    Joe,

    I have tested the ADS54J66EVM with a ZC706 using both LMFS settings of 4841 and 4421 with no problems. Example of the source code used can be found under the TSW14J10EVM product folder on the TI website. If you would like, send me your ADC configuration file and the mode you are trying to test and I can duplicate this test with our setup.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 80 points

    Hi Jim,


    Thanks for trying it.    I have attached the configuration files I am using.      It is setup to run Mode 8  (4421) with a sample rate of 50Msps which has a line rate of 1Gbps.   The GTX reference clock is set to 250MHz.

    ADC settings file:

    LMK04828
    0x10F 0x66
    ADS54Jxx_ANALOG  
    0x0000 0x81
    0x8053 0x80 // divide by 2
    0x8039 0xC0 // always write 1
    0x8059 0x20 // always write 1
    ADS54Jxx_DIGITAL  
    0x6800f7 0x01 // digital top reset
    0x680042 0x00 //nyquist zone select 1st Nyquist = 0
    0x68004E 0x80 //2rd nyquist validity
    0x680000 0x01 // reset digital page 6800h
    0x680000 0x00 // clear reset
    0x614100 0x08 // bypass mode - Mode 8
    0x6A0016 0x02 // JESD PLL mode 40x
    0x690000 0xC0 // set CTRL K, JESD MODE EN
    0x690006 0x0F // set K to 16
    0x690001 0x01 // JESD MODE 20x
    // 0x690002 0x40 // set Testmode K28.5
    LMK04828
    0x10F 0x06

    LMK04828 settings file

    LMK04828  
    0x00 0x00
    0x02 0x00
    0x100 0x01
    0x101 0x55
    0x103 0x02
    0x104 0x20
    0x105 0x00
    0x106 0x70
    0x107 0x06
    0x108 0x05
    0x109 0x55
    0x10B 0x00
    0x10C 0x20
    0x10D 0x00
    0x10E 0x70
    0x10F 0x06
    0x110 0x08
    0x111 0x55
    0x113 0x00
    0x114 0x00
    0x115 0x00
    0x116 0x71
    0x117 0x01
    0x118 0x08
    0x119 0x55
    0x11B 0x00
    0x11C 0x00
    0x11D 0x00
    0x11E 0x71
    0x11F 0x01
    0x120 0x08
    0x121 0x55
    0x123 0x00
    0x124 0x00
    0x125 0x00
    0x126 0x71
    0x127 0x01
    0x128 0x08
    0x129 0x55
    0x12B 0x00
    0x12C 0x00
    0x12D 0x00
    0x12E 0x71
    0x12F 0x01
    0x130 0x02
    0x131 0x55
    0x133 0x02
    0x134 0x00
    0x135 0x00
    0x136 0x70
    0x137 0x11
    0x138 0x40
    0x139 0x03
    0x13A 0x01
    0x13B 0x00
    0x13C 0x00
    0x13D 0x08
    0x13E 0x03
    0x13F 0x18
    0x140 0x03
    0x141 0x00
    0x142 0x00
    0x143 0x11
    0x144 0xFF
    0x145 0x00
    0x146 0x10
    0x147 0x12
    0x148 0x02
    0x149 0x42
    0x14A 0x02
    0x14B 0x16
    0x14C 0x00
    0x14D 0x00
    0x14E 0x00
    0x14F 0x7F
    0x150 0x03
    0x151 0x02
    0x152 0x00
    0x153 0x00
    0x154 0x78
    0x155 0x00
    0x156 0x96
    0x157 0x00
    0x158 0x96
    0x159 0x00
    0x15A 0x78
    0x15B 0x14
    0x15C 0x20
    0x15D 0x00
    0x15E 0x00
    0x15F 0x0E
    0x160 0x00
    0x161 0x02
    0x162 0x45
    0x163 0x00
    0x164 0x00
    0x165 0x0C
    0x166 0x00
    0x167 0x00
    0x168 0x0C
    0x169 0x59
    0x16A 0x20
    0x16B 0x00
    0x16C 0x00
    0x16D 0x00
    0x16E 0x16
    0x17C 0x15
    0x17D 0x0F

  • 0 in reply to Joseph Mead
    TI__Guru* 91947 points

    Joe,

    Can you try changing address 0x690001 to 0x80 instead of 0xC)? With the setting at  0xC0 I could never get the link to synchronize. Did you mean to say the sample rate was 500MSPS? The post has 50MSPS.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 80 points

    Hi Jim,

    Do you mean address 0x690000?    I have 0x690001 set to 0x1

    I was able to make some progress, if I disable rxcommaalignen on the Xilinx GTX receiver after the ILAS phase then the data I receive from the ADC looks perfect with any signal amplitude.     Does the ADS54J66 transmit alignment characters in the data stream?   I seem to be receiving K characters (although they are not always K28.7 or K28.3 codes as described in the JESD spec.) which was causing the receiver to do a re-alignment which was breaking things.      The other strange thing is I always get disparity errors, yet the received data looks perfect.

    I slowed down the sample rate to 50MSPS so that the JESD link would only be running at 1Gbps, so that I could maybe rule out signal integrity issues.   When I probe the signals with a high speed differential probe, they look great.    


    Thanks,

    Joe

  • 0 in reply to Joseph Mead
    TI__Guru* 91947 points
    Joe,
    Ignore the last address write I mentioned. This was incorrect. Are you still having issues with this? If you think there as an issue with the ILA data, can you send a chipscope screen shot of all the lanes showing this problem?
    Regards,
    Jim
  • 0 in reply to jim s
    Prodigy 80 points

    Hi Jim,


    Yes, I am still having issues.   The first screenshot is showing the CGS, ILA and data phases.   I seem to be getting all the data correct but am getting RXDISPERR asserted from the Xilinx GTX block which is strange.   When the ADC enters the data phase, I can see a nice sine wave output. 

    Then every so often I appear to receive a K code from the ADC.   Attached is a screenshot of receiving a K28.7 (0xFC).    This is causing the GTX receiver to try to realign the data and then the data no longer looks correct.   I can disable the realignment process after the ILA phase and then the data stays fine.    I keep thinking this could be a signal integrity issue, but I get the same results even when I slow the sample rate to 50Msps, which corresponds to a 1Gbps link rate.   I've probed the signals with a high speed diff probe and they look great.    Could the ADC be outputting K codes periodically?

  • 0 in reply to Joseph Mead
    TI__Guru* 91947 points

    Joseph,

    What value is set for bit 1 on address 0x0 in page 0x6900 (frame alignment) when you are having this issue? If it is set to "1", can you try it with it set to "0" and let us know what you report? The K28.7 should occur when the last octet in 2 successive frame are equal per the JESD standard. So I would expect these to appear randomly.

    Regards,

    Jim