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DAC80508: tCSIGNORE - Figure 62/63 in DAC80508 datasheet

Part Number: DAC80508

tCSIGNORE is defined as "SCLK falling edge to CS ignore", but it is very clearly drawn to the middle of an SCLK cycle in Figures 62 and 63.

Can someone please tell me which one is correct?

Also, can someone tell me why tCSIGNORE is needed at all? It looks like the falling edge of SCLK is already constrained by the tCSS (chip select falling to SCLK falling setup time), so as long as it isn't violated tCSIGNORE would be redundant. Am I missing something? 


  • Travis,

    The requirement is with respect to the last SCLK falling edge to the CS rising edge. Basically indicating that if CS were to rise too soon the interface would not have had time to latch the final data bit, and therefore the interface would not see the complete frame. The illustration is from the last falling edge to the CS rising edge.

  • ...actually, I think I let my understanding of the mechanic get in the way of the problem with the datasheet...

    The diagram really should be drawn with respect to the CS rising edge, not the falling edge I highlighted. In any case, the intention is as I described.

    I will give feedback to the datasheet owner.