ADS54J60: Changing the sample rate yields to spurs

Nissan Luzon

Part Number: ADS54J60
Other Parts Discussed in Thread: , LMK04828, LMK04616EVM, LMK04616

Hello,

I use ADS54J60EVM with TSW14J56 in order to decide the optimal conditions to operate the ADC.

I followed the instructions in slau629i and managed to receive successfully digital samples in HSDC GUI @ 983.04 MSPS with SFDR = 90 dBFS.

Then, I tried to change the ADC sample rate to different value using the following steps:

Loading the “LMK_Config_Onboard_409p6_MSPS.cfg” file, verifying D2 is lit, pressing SW1 to reset the ADC, loading the “ADS54J60_LMF_4244.cfg” file.
Opening the HSDC GUI and select in ADC drop-down menu the “ADS54J60_LMF_4244” option, set the “ADC Output data rate” to 409.6M and reset the board.

As before, I received the digital samples, however, now the FFT contains much more spurs and the SFDR decreased dramatically to 45 dBFS.

I repeat the steps above for 819.2 MSPS, and the spurs are still exist. However, setting the sample rate to 491.52 MSPS yields to SFDR ~ 90 dBFS.

My questions are:

Are the steps mentioned above correct?
If so, why is there such a significant difference between the results?
What is the right way to configure the ADC to operate in 409.6 / 819.2 MSPS without all those spurs?

Thanks in advance,

over 7 years ago

0 Brian Kincaid over 7 years ago

TI__Intellectual 2750 points

Hello Nissan,
I have sent this over to an engineer that works with the ADS54J60
Regards,
Brian

0 jim s over 7 years ago in reply to Brian Kincaid

TI__Guru* 91947 points

Nissan,

The LMK was optimized for an output clock setting of 983.04MSPS. Due to this, the phase noise of the LMK will be higher when using the other clock outputs due to different settings required to generate the lower clock rates. To optimize the LMK for these other rates, one would have to change the external loop filter components, the internal loop filter values, the pre-scalar value, the N-divider value and the charge pump gain. Please consult the LMK04828 data sheet for more information regarding this. Another option to use the board as is would be to run the LMK in clock distribution mode and bring in an external clock source.

Regards,

Jim

0 Nissan Luzon over 7 years ago in reply to jim s

Prodigy 70 points

Hi Jim,

Thank you very much for the detailed response. This is match with the results we had which were the best @ 983.04M.

Considering your suggestion to run the LMK in clock distribution mode - We have in addition an LMK04616EVM that I think could be used as 819.2M clock source for the LMK at ADS54J60EVM.

Given a 409.6M sine wave as the reference for the LMK04616EVM, could you please advise us what should be the EVM boards configuration (registers & connection) such that the ADS54J60 will be operate @ 819.2M with its LMK at distribution mode?

Best Regards,

0 jim s over 7 years ago in reply to Nissan Luzon

TI__Guru* 91947 points

Nissan,

I am not familiar with the LMK EVM. Please contact the High Speed Clocking forum for help with programming this board. The output of the LMK EVM will connect to J6 of the ADC EVM and you will then select the mode called "LMK_Config_External_Clock.cfg" from the ADC GUI to configure the LMK for clock distribution mode.

Regards,

Jim

0 Nir Flysher over 7 years ago in reply to jim s

TI__Expert 3367 points

Dear Jim,
Nissan wants to work with fs of 409.6MHz.
At this freq the interleaving fs/4 spur is huge and gets to -45dBc which is way over the interleaving spur described in the datasheet at higher frequencies.
We understand the ADC is optimized for a fs of 700-1000MSPS however we didn't expect to see a -45dBc interleaving spur.
As a result I wanted to ask the following questions :
1. Is it possible to configure/calibrate the ADC to have better performance at lower frequencies (below 500MSPS) ?
2. If they want to work in sub 500MSPS, is it possible to force the chip to interleave by 2 (instead of by 4) in order to loose the fs/4 spur ?

Best regards,
Nir.

0 jim s over 7 years ago in reply to Nir Flysher

TI__Guru* 91947 points

ADS54J60_Ext_409.6M_70M_IF.pptxNir,

Is this seen on the TI EVM or the customers board? On the TI EVM, the LMK is optimized for the highest sample rate which is 983.04Msps. To get better results at 409.6Msps, the LMK internal and external charge pump loop filters would need to change along with the PLL2 settings. Attached are plots from two captures. One is using the LMK in clock buffer distribution mode with a external 409.6MHz clock brought in and the second is using the LMK as is with a ADC output clock at 409.6Msps. What frequency is the input at when they see this large spur? You cannot do an interleave by 2 with this part.

Regards,

Jim

0 Nir Flysher over 7 years ago in reply to jim s

TI__Expert 3367 points

Jim,

Thanks for looking into this and sending the plots.

Unfortunately we see different results on the ADS54J60EVM when using external 409.6MHz clock from a signal generator followed by a bandpass filter.

They're trying to sample Fin=300MHz with fs=409.6 and the fs/4 spur we observe is ~45dBc.

Can you advise on how to configure the on-board LMK and loop filter in order to achieve better results ?

Nissan,

Can you please attached the plots and a short description of your setup ?

Regards,

Nir

0 Timothy T over 7 years ago in reply to Nir Flysher

TI__Mastermind 28560 points

Hello Nir,

As stated above, the on board LMK04828 is optimized for 983.04 MHz. This means a VCO1 frequency of 2949.12 MHz using a VCXO of 122.88 MHz.

To sample at 409.6 MHz at VCO0 frequency of 2457.6 MHz should be used with a 122.88 MHz phase detector frequency. This involves programming PLL2 N = 10 and PLL2_P = 2. Are these the settings you are using? I would expect them to be fairly optimized. The total N divide is smaller, but the Kvco is also smaller so the loop filter scales fairly well.

Were you trying to optimize a filter for LMK04616 also for testing?

73,
Timothy

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ADS54J60: Changing the sample rate yields to spurs