• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 1156 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC7760: Slew rate specification not reached, slew rate too low, settling time too high. rise time too slow

Simon Wyss
Prodigy 50 points
Part Number: DAC7760

I measured the slew rate of the voltage and current output during full scale jumps: 0 to 10V and 0 to 20mA.
My measurement results were in the are of 100us (voltage mode) and 500us (current mode) rise time.
According to the data sheet the typ settling time in voltage output mode is 22us, in current mode 25us.

Furthermore, I measured rise time, which is measured from 10% to 90% of the edge. Settling time is specified as to 0.03% FSR. Therefore, the settling time in my case would be even more. But rise time is simpler to measure with an Oscilloscope.

The slew rate control/limiter is disabled in the control register (address 0x55): written content: 0x3001 = 0011 0000 0000 0001
Therefore, the slew rate should be at its maximum.

The measurements were almost independent of the load at the output (changes some us).
Fall-Time was 10% longer than Rise-Time, but that is fine for me.

Do you have any advice for me?
Did I something wrong?
Are there some hints in the data sheet, which I overlooked?

Measurement Results:

Rise-Time (10% to 90%) Voltage Output: 
Open Load: 90 - 112us
1k Load: 96 - 115us

Rise-Time (10% to 90%) Current Output: 
Short Circuit Load: 460 - 600us
300R Load: 490 - 620us

Voltage Mode, Rise Time, 106us

Voltage Mode, Fall-Time, 136us


 

 

Current Mode, Rise Time, CH1: Voltage measurement, CH2: current clamp, 575us, 


 

Current Mode, Fall Time, CH1: Voltage measurement, CH2: current clamp, 527us


  • 0
    Prodigy 50 points

    I am using the DAC in combined voltage and current output mode. I am aware that some current will flow into the +VSENSE in current output mode.
    This will reduce the accuracy by fraction of percent.

    However, there should be only minimal influence on the slew-rate / rise time / settling time.

    My measurements are factor 5 to 20 away from the specification in the data sheet. (measured 100us - 500us vs specification of 20us)

    I am using almost the same schematic as in the application note.

    combined output configuration:

    Changes in my schematic vs application note:
    220nF capacitor instead of 100nF at the output
    Ferritebead moved directly to the output.
    Single 24V supply instead of 15V dual supply.

  • 0 in reply to Simon Wyss
    TI__Expert 5820 points
    Hi Simon,

    The settling time for the voltage output as listed in the datasheet is with 2kOhm || 200pF load (listed at the top of 7.6). Refer to figure 39 which shows VOUT settling time vs. load capacitance. With a 220nF (C83) load and CMP = 470pF this plot indicates around 100us settling time which roughly agrees with your measurement. The same applies to the current output as the settling time is specified only for a 300Ohm resistive load.

    Thanks,
    Garrett
  • 0 in reply to Garrett Satterfield
    Prodigy 50 points

    Hi Garrett

    Thank you very much for your support!

    However, would be nice, if there is also a figure for the settling time in current mode. 
    I think, you skipped it, because it would be even worse ;-)