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ADS1256: Is DRDY synchronoised to the master clock?

IainRist
Intellectual 711 points
Part Number: ADS1256

The DRDY signal is asserted to indicate a conversion is complete. How is the DRDY signal related to the master clock? Does the DRDY signal transition on a master clock edge?

  • 0
    TI__Mastermind 44680 points

    Hi IainRist,

    One of the master clock edges should trigger /DRDY, but there are going to be some delays (both internal and external) that will like cause the clock and /DRDY edges to be out of alignment

    Are you trying to use the /DRDY signal to decide when to issue a /SYNC pulse, or is there another reason for needing to know if these clock edges are aligned?

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Intellectual 711 points

    I am indeed trying to use the /DRDY signal to decided when to issue a /SYNC pulse. I have multiple ADCs clocked by the same clock and need to synchronise them. My host does not have access to the ADC master clock so I am looking for a way to synchronise the /SYNC pulse and the master clock.

  • 0 in reply to IainRist
    TI__Mastermind 44680 points

    Hi IainRist,

    Instead of using the /SYNC pin with it's strict timing requirement, would you be able to use the SYNC SPI command and issue it to all devices at once?...That would be be my recommended solution to synchronize the ADCs.

    Otherwise, you'd probably need to use a logic circuit (i.e. D flip-flop) to re-clock the SYNC pulse so that it aligns with the master clock rising edge.

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Intellectual 711 points

    Hi Chris,

    For the next board iteration I will definitely use an external circuit to synchronise the /SYNC and clock edges, but I am looking for a method for my current design. Unfortunately the possible single clock difference that can arise from the SPI SYNC command (across 4 ADCs) has an effect on my system.

    Concerning the delays between the clock edge and the /DRDY edge:

    1. What is the distribution of the delays for a single chip, e.g. gaussian with mean 20 ns and standard deviation 10 ns?
    2. Is the distribution of delays the same for all chips or are there widely differing means and standard deviations?

    Thanks,

    Iain

  • 0 in reply to IainRist
    TI__Mastermind 44680 points

    Hi Iain,

    Trace delays might indeed cause the the ADCs to be out of sync by a clock period. However, this can also occur while using the SYNC pulse if the CLKIN and /SYNC trace lengths are not matched between ADCs.

    It usually isn't an issue in most low-frequency applications for multiple delta-sigma ADCs to be out of sync by several clock periods...A higher degree of synchronization is only needed if you need to be able to correlate the timestamps of when an event took place on multiple channels or locations. Since the ADS1256 output is filtered through a SINC5 filter, the frequency response is significantly attenuated at higher frequencies, making pulse or step detection a bit more difficult. In these cases, you'd likely want to have a wide band filter with a flat pass-band to better detect these pulses.

    Unfortunately, I don't have any timing data to be able to correlate /DRDY to the CLK; however, by looking at the t7 delay time I would expect the internal propagation delay of CLK to /DRDY to be on the same order of magnitude. Since this is exceeds t16B by 2x, I can't recommend /DRDY as a reliable indicator of the rising CLK edge.

    All I can recommend to do is try the SYNC command, and if you want, try out your proposed solution of triggering the /SYNC pulse from /DRDY; though I only recommend the former because it is safer. Missing the timing of the /SYNC pulse to the ADS1256 might cause the device to become unresponsive and require you to reset it to restore proper operation.

    Best regards,
    Chris