ADS5400: Maximum clock input to an unpowered device.

Hi Charles,

We are taking a look into your question, and will be back with you soon.

Best Regards,

Dan

Hey Charles,

Leaving the device powered down while applying a clock input will stress the ESD diodes. I dont think this will be detrimental unless the voltage surpasses the absolute max found in the datasheet.  Reference the following picture. 

Yusuf

I had already examined the data sheet. The data sheet snapshot provided is not complete. The referenced Note 2 states under nominal supplied input voltage. If the ESD diodes are stressed that could alter the interface characteristics significantly and cause detrimental behavior. This is what I am attempting to understand. When discussing ESD damage it would not only include voltage but current capability as well.

The absolute maximum specifications do not address power off and do not make sense relative to a power off condition. For example, the specification states that the minimum of the clocks to gnd is 0.5 to 4.5. Obviously, with the device off and nothing driving it, this cannot be met. Most of the time, these specifications are written w.r.t. VDD itself. In the A/Ds case, they assume power is applied and within certain limits.

Then there is the second requirement of the voltage DC between the two clock pins must be a minimum of 2V and maximum of 3V. I do not understand this one at all. The clock signals is driven with an AC coupled  balun. I would expect 0V DC between the pins.

CLKINP, CLKINN to GND(2) Voltage difference between pin and ground 0.5 4.5 V

Voltage difference Continuous AC signal 1.1 3.9 V

CLKINP to CLKINN(2) between pins, common

mode at AVDD5/2 Continuous DC signal 2 3 V

Charles