• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 784 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDC112: Some wrong about my DDC112 data result,need your help!

user199770
Prodigy 55 points
Part Number: DDC112

Hello everyone:

    I use stm32F1 to drive the DDC112, I get the 12Mhz CLK for DDC112 based on stm32F1 PWM output. And also get the CONV based on stm32F1 another PWM out (50% duty). When I set the CONV time is 1000ms,the it should work as continue mode, No signal is connect to DDC112,I get the below result using stm32 mcu SPI function:

ch1:-36.05 ch2:-46.49fA
ch1:-58.68 ch2:-48.85fA
ch1:-35.48 ch2:-45.22fA
ch1:-59.11 ch2:-48.99fA
ch1:-34.12 ch2:-44.33fA
ch1:-56.33 ch2:-50.54fA
ch1:-34.87 ch2:-47.53fA
ch1:-58.35 ch2:-49.18fA
ch1:-36.05 ch2:-46.64fA
ch1:-58.64 ch2:-50.68fA
ch1:-34.12 ch2:-45.84fA
ch1:-57.60 ch2:-49.55fA
ch1:-36.09 ch2:-49.22fA

We can see the CH1 result has stage,-36->-58->-34,I do not konw why. And CH2 seemed only a little.

When I set the CONV time is 50ms integrating time,also no input to DDC112, data is below:

ch1:-470.59 ch2:-367.06fA
ch1:-477.18 ch2:-424.47fA
ch1:174.12 ch2:89.41fA
ch1:169.41 ch2:106.35fA
ch1:164.71 ch2:93.18fA
ch1:134.59 ch2:41.41fA
ch1:-442.35 ch2:-312.47fA
ch1:-419.77 ch2:-249.41fA
ch1:-378.35 ch2:-174.12fA
ch1:30.12 ch2:-236.24fA
ch1:2.82 ch2:-297.41fA
ch1:-15.06 ch2:-358.59fA
ch1:-291.76 ch2:64.00fA
ch1:-278.59 ch2:64.00fA
ch1:-265.41 ch2:38.59fA
ch1:-306.82 ch2:-1.88fA
ch1:9.41 ch2:-293.65fA
ch1:40.47 ch2:-228.71fA
ch1:79.06 ch2:-140.24fA
ch1:-432.00 ch2:-299.29fA
ch1:-467.77 ch2:-370.82fA
ch1:-475.29 ch2:-437.65fA
ch1:-489.41 ch2:-434.82fA
ch1:176.00 ch2:83.76fA

We can see there is big fluction, can you help me?

  • 0
    TI__Mastermind 49916 points
    Hello,

    Welcome to TI E2E forum!

    How do you provide the voltage reference (VREF) to the device?
    What is the DCLK frequency and the range setting?
    Have you tried the TEST mode?
  • 0 in reply to Praveen Aroul
    Prodigy 55 points

    Hello Praveen:

        Thanks for your reply.

    1.After check:My VREF is very good,and the chip and circuit is the same as the datasheet.

    2.My DCKL frequency is 9MHz, it is created by stm32F1 SPI peripheral and 8Xprescaled from 72MHz to 9MHz.

    3.My DDC112 range setting is rang1(12.5pF).

    4.My data result using TEST mode as below

    test condition:(1.two channel and unit is fA;  2.Integrating time is 1000ms; 3.range1;):

    ch1:13628.01 ch2:13628.11fA
    ch1:13397.00 ch2:13402.51fA
    ch1:13628.44 ch2:13629.47fA
    ch1:13397.80 ch2:13402.84fA
    ch1:13627.92 ch2:13628.95fA
    ch1:13396.72 ch2:13403.21fA
    ch1:13628.53 ch2:13628.15fA
    ch1:13396.58 ch2:13402.18fA
    ch1:13627.97 ch2:13629.75fA
    ch1:13397.10 ch2:13403.12fA
    ch1:13628.58 ch2:13629.90fA
    ch1:13397.85 ch2:13402.22fA
    ch1:13627.50 ch2:13628.86fA
    ch1:13397.00 ch2:13401.33fA
    ch1:13627.97 ch2:13629.24fA
    ch1:13397.52 ch2:13402.93fA

    test condition:(1.two channel and unit is pA;  2.Integrating time is 10ms; 3.range1;):

    ch1:1341.40 ch2:1341.93pA
    ch1:1364.61 ch2:1364.79pA
    ch1:1341.51 ch2:1341.89pA
    ch1:1341.47 ch2:1341.97pA
    ch1:1364.60 ch2:1364.68pA
    ch1:1341.44 ch2:1341.88pA
    ch1:1364.60 ch2:1364.67pA
    ch1:1341.49 ch2:1341.97pA
    ch1:1341.52 ch2:1341.98pA
    ch1:1364.53 ch2:1364.69pA
    ch1:1364.58 ch2:1364.67pA
    ch1:1364.59 ch2:1364.79pA
    ch1:1341.46 ch2:1341.97pA
    ch1:1341.42 ch2:1341.89pA
    ch1:1341.46 ch2:1341.97pA
    ch1:1364.54 ch2:1364.80pA
    ch1:1364.62 ch2:1364.69pA
    ch1:1341.42 ch2:1341.98pA
    ch1:1364.65 ch2:1364.80pA
    ch1:1341.44 ch2:1341.99pA
    ch1:1364.63 ch2:1364.79pA
    ch1:1364.58 ch2:1364.68pA
    ch1:1341.48 ch2:1342.00pA
    ch1:1364.62 ch2:1364.67pA
    ch1:1341.39 ch2:1341.97pA
    ch1:1364.61 ch2:1364.67pA
    ch1:1341.44 ch2:1341.98pA
    ch1:1341.38 ch2:1341.99pA
    ch1:1364.56 ch2:1364.78pA
    ch1:1341.42 ch2:1341.98pA
    ch1:1364.58 ch2:1364.71pA
    ch1:1341.46 ch2:1341.94pA
    ch1:1341.45 ch2:1341.94pA

    There is fluction still, why?

    Some one tell me it is because 50Hz power noise. But I think that  the 1000ms integrating time should average this noise.

    Waiting for your help.

    Thanks

  • 0 in reply to user199770
    TI__Mastermind 49916 points

    Hi Lv Liang,

    In test mode, there is an inherent difference between the “A” and “B” side values of the test mode charge packet.
    The Side A is typically ~0.2 pC larger than Side B.

    Please refer to the application note on DDC112 test mode.
    www.ti.com/.../sbaa025.pdf

    As explained in the app note: "The A and B sides of a channel use the same CTEST. Due to the nature of the switching arrangement, there is a small imbalance in the charge injection between sides A and B during test mode. This imbalance results in slightly different effective sizes for the side A and B test packets. Typical mismatch between side A and B charge packets is ≈0.2pC."

    Your test data also seems to suggest the same.
    One side data is 0.2pC larger than the other side.