Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 48 subscribers
  • Views 625 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC14X250EVM: JESD Subclass 0 Connection

John Fedak
Expert 6715 points
Part Number: ADC14X250EVM
Other Parts Discussed in Thread: ADC14X250, TIDEP0060, RFSDK

Hi Team,

My customer is looking at the TIDEP0060 design and connecting the ADC14x250 to the K2L, and has the following questions:

We are trying to understand the role of SYSCLK coming from the Keystone. Is it necessary for this clock to be synchronous with the ADC sample clock if we are not trying to use any other devices?

We are attempting to use the ADC14X250 eval board with the RFSDK to test the JESD link to the Keystone. The reference design uses a DAC and Deterministic Latency Card, and the latency card uses the SYSCLK from the Keystone to generate the ADC and DAC device clocks. Is this necessary even if we want to use subclass 0 (no deterministic latency) and the ADC by itself with the Keystone, without the DAC and Latency cards connected?

Related to this, the ADC datasheet states that it “supports most subclass 0 requirements, but is not strictly subclass compliant” (pg 27 of datasheet). Is it possible to get more details about what that means exactly?

Thank you!

Regards,

~John

  • 0
    TI__Genius 12780 points
    Hi John,

    We are taking a closer look at your question, and will be back with you soon.

    Best Regards,

    Dan
  • 0 in reply to dBrock
    TI__Mastermind 44560 points

    Hi John

    I haven't found a lot of additional detail regarding subclass 0 operation.

    My expectation given what I have found is that it the ADC14X250 can be used in pseudo subclass 0 given the following constraints:

    1. SYSREF must be pulsed at least once after the ADC is powered and clocked. This is required to reset the internal digital circuitry and to initialize the JESD204B transmit logic. 
    2. ~SYNC must be provided from the data receiver to control link initialization and re-initialization, but cannot be used to control LMFC timing.

    If I find more information I'll respond with the additional details.

    Best regards,

    Jim B