Other Parts Discussed in Thread: ADC14X250, TIDEP0060, RFSDK
Hi Team,
My customer is looking at the TIDEP0060 design and connecting the ADC14x250 to the K2L, and has the following questions:
We are trying to understand the role of SYSCLK coming from the Keystone. Is it necessary for this clock to be synchronous with the ADC sample clock if we are not trying to use any other devices?
We are attempting to use the ADC14X250 eval board with the RFSDK to test the JESD link to the Keystone. The reference design uses a DAC and Deterministic Latency Card, and the latency card uses the SYSCLK from the Keystone to generate the ADC and DAC device clocks. Is this necessary even if we want to use subclass 0 (no deterministic latency) and the ADC by itself with the Keystone, without the DAC and Latency cards connected?
Related to this, the ADC datasheet states that it “supports most subclass 0 requirements, but is not strictly subclass compliant” (pg 27 of datasheet). Is it possible to get more details about what that means exactly?
Thank you!
Regards,
~John