DDC264: DDC 264 FPGA firmware

Hi Sebin,

I’ve looked for other resources and reached out to other engineers who used to support this device and unfortunately we do not have any more documentation on the FGPA firmware.

The firmware captures x samples, where x is some power of 2 times some power of 2 channels. It stores it in RAM, and then when the capture is complete, it stops talking to the DDC and just shifts the data back through the USB interface to the PC.

Some notes on the FPGA firmware that you can use while looking at the code.

There are 3 system clocks
FPGA clk 80mHz generated by on board oscillator
DDC_CLK 10Mhz generated by FPGA CLK_GEN
IF_CLK 33Mhz for usb interface generated by USB chip

CLK_GEN and CONV_GEN modules are used to generate the CLK and CONV signals.

DDC_ACQ_CONTROL module sets up the data acquisition, sets up the FSM to ignore DVALIDs and number of samples to read.

DDC_DATA_CAP module does the actual data acquisition and handles sending DCLKS to the devices.

DDC_DATA_FIFO module places the captured data into the RAM memory.

RAM_TO_USB module pulls the data from RAM memory and sends the data to PC GUI.

Hope this helps.

We will not be able to share the source code of DDC264 EVM GUI.