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ADC12J1600: Deterministic latency between startups.

Part Number: ADC12J1600
I am trying to make the ADC12J1600 work with deterministic latency between startups. A pulsed sysref with the frequency of 12.5 MHz (1/128 of the device clock) is used. That frequency is a sub harmonic of the LMFC. I have also tried a continuous sysref. The JESD204B link start up and the FPGA receives data from the ADC, but the values of the RBD count for each start up seams to be random and span the whole range from 1 to 32. I can also observe this random latency in my data. Also the Dirty Capture (bit 7) is set to high and the SysRefDet (bit 6) is set to low in register CLKGEN_1 (0x031). According to the documentation this indicates that setup or hold is not met for SYSREF. I have tried to cycle through all the different delays of SYSREF by using RDEL (3-0) in register CLKGEN_2 (0x032). I have also tried to add some external delay to either the SYSREF or device clock combined with RDEL. The result are always the same, Dirty Capture is high, SysRefDet is low and RBD count is random. Do you have any suggestions of what may be wrong or how to further investigate to problem?
We use the following settings: L=1, M=2, F=4, N=15, N'=16, S=1, K=32, DDR=0, P54=1
Decimation = 32. Device clock is 1600MHz. Sysref 12.5MHz pulsed or continuous.
  • Hi user
    For that configuration the maximum LMFC (local multi-frame clock) frequency is 1.5625 MHz.
    F_LMFC = F_Bit / (F * K * 10 bits per octet)
    For F_CLK = 1600 MHz, DDR = 0, P54 = 1 F_Bit = 1600 MHz * 1.25 = 2000 MHz.
    Therefore F_BIT = 2000 / (4 * 32 * 10) = 1.5625 MHz
    Please try changing the SYSREF frequency to 1.5625 MHz or a sub-harmonic of that frequency and let me know if the behavior improves.
    Best regards,
    Jim B
  • I tried changing the frequency of SYSREF to 1.5625 MHz, but it did not change the behavior. I did not try a subharmonic of 1.5625 MHz since the HW is not able to produce that low frequency for SYSREF.

  • Hi user
    If the SysRefDet bit is never being set that indicates that no valid SYSREF rising edges are being detected.
    Please confirm you are DC-coupling the SYSREF signal from clock source to ADC12J1600. If possible please send a schematic showing the connections between SYSREF source and the ADC SYSREF inputs.
    What is the common mode voltage and differential swing of the SYSREF signal at the ADC12J1600 SYSREF inputs. If the common mode voltage is too high this may cause problems with proper detection.
    What is the value written to CLKGEN_0 (address 0x030). Make sure both bit 7 and bit 6 are set to enable the SYSREF receiver and SYSREF processing.
    DC_LVPECL_SYSREF_en may need to be set depending on the type of SYSREF source and the connection/termination method.
    Best regards,
    Jim B
  • Unfortunately the person who designed the hardware and the project leader decided that I could not share any information about the hardware on a public forum. All I can say it that is AC-coupled. I can give no schematic nor any voltage measurement.

    Both bit 7 and 6 in register CLKGEN_0 (0x30) are set. First both bits are set to 0, then bit 7 is set high after a delay and bit 6 is set high after additional delay.
  • I understand.
    For an AC-coupled system you will need to operate using one of the two following scenarios:
    1) Run a continuous SYSREF. A continuous SYSREF will ensure the AC-coupled SYSREF inputs are biased at the proper voltage.
    2) Run a burst mode SYSREF. The burst must be long enough to properly bias the SYSREF receiver before SYSREF processing is enabled. Once the LMFC timing is properly set SYSREF processing can be disabled, and then the SYSREF burst can be turned off. If the link needs to be re-synchronized this process must be repeated.
    Can you send me the entire register write sequence you are sending to the ADC12J1600 device? I will check it and recommend any changes needed.
    If you can't share the settings I will provide a recommended configuration write sequence tomorrow.
    Please ensure the applied SYSREF frequency is at F_SYSREF = F_BIT/(4 * 32 * 10) for that decimation and lane rate setting.
    Best regards,
    Jim B
  • Hi again

    Here is the configuration write sequence that I recommend for the ADC.

    • Power up ADC
    • Power up clock sources
    • Turn on DEVCLK and SYSREF to ADC

    ADC12J1600 initialization

    • Write 0x0021 0x00 // Initiate reset of all registers
    • Write 0x0021 0x01 // De-assert reset
    • Write 0x0201 0xFC // Scrambler on, KM1 = 31, SDR, JESD disabled
    • Write 0x0040 0x04 // Set serializer pre-emphasis for high speed PCB
    • Write 0x0066 0x03 // Foreground calibration mode with timing optimization enabled
    • Write 0x0208 0x07 // Change over-range processing to longest interval
    • Write 0x0051 0x84 // Calibration optimized for large signals
    • Write 0x0200 0x17 // 6.02dB gain, decimate-by-32
    • Write 0x0202 0x80 // P54 PLL on, Single Ended SYNC, Normal data mode
    • Write 0x0030 0xC0 // SYSREF receiver enabled, SYSREF processor enabled
    • Write 0x0201 0xFD // Scrambler on, KM1 = 31, SDR, JESD enabled

    ADC SYSREF delay calibration procedure

    • Write 0x032 0x80 // Set RDEL to minimum

    Begin loop

    • Write 0x030 0xF0 // Clear dirty capture and SysRefDet
    • Write 0x030 0xC0 // Clear dirty capture and SysRefDet
    • Read 0x031 // Check state of SysRefDet and Dirty Capture bits. If SysRefDet = 1 then record Dirty Capture Bit status and proceed to next step. If SysRefDet=0 then exit on error due to no SYSREF detection.
    • Read 0x032 // Check lower nibble, if F then exit loop, else increment lower nibble and
    • Write 0x032 0x8x // Set RDEL to next higher value

    Back to beginning of loop

    Evaluate recorded values for Dirty Capture at reach RDEL setting. There will be a range of RDEL settings where Dirty Capture is set. Select the RDEL setting that is farthest away from the middle of the Dirty Capture range as possible.

    • Write 0x032 // 0x8y  where y is the selected RDEL value
    • Write 0x030 0xF0 // Clear dirty capture and SysRefDet
    • Write 0x030 0xC0 // Clear dirty capture and SysRefDet
    • Read 0x031 // Check state of SysRefDet and Dirty Capture bits. Confirm SysRefDet=1 and Dirty Capture = 0

    LMFC is now set with clean capture of SYSREF

    • Write 0x0201 0xFC // Scrambler on, KM1 = 31, SDR, JESD disabled
    • Write 0x0050 0x0E // Initiate a foreground calibration
    • Write 0x0201 0xFD //  Scrambler on, KM1 = 31, SDR, JESD enabled

    Enable FPGA JESD204B receiver at this point, once ADC JESD204B transmitter is enabled and will be stable

    If burst mode SYSREF is being used (to minimize SYSREF related spurs in ADC spectrum) then do the following before stopping SYSREF output from the clock source

    • Write 0x0030 0x80 // SYSREF receiver enabled, SYSREF processing disabled
    • Turn off SYSREF at clock source

    Reverse the above process if SYSREF must be re-captured to re-align the ADC due to a link disturbance or error.

    I hope this sequence is clear enough.

    Let me know if you have any questions.

    Best regards,

    Jim B

  • This is the sequence.

    First this is blob of data is written.
    Addr, data
    wr: 0x0021, 0x00
    wr: 0x0021, 0x01
    wr: 0x0030, 0x00
    wr: 0x0033, 0xC3
    wr: 0x0040, 0x04
    wr: 0x0066, 0x03
    wr: 0x002B, 0x13
    wr: 0x0208, 0x07
    wr: 0x0051, 0x84
    wr: 0x0201, 0xFC
    wr: 0x0200, 0x37
    wr: 0x0202, 0xC0
    wr: 0x0206, 0xFF
    wr: 0x0207, 0xFF
    wr: 0x0208, 0x07
    wr: 0x020C, 0x01
    wr: 0x020D, 0x00
    wr: 0x020E, 0x00
    wr: 0x020F, 0x00
    wr: 0x0210, 0x00
    wr: 0x0211, 0x00
    wr: 0x0212, 0x40
    wr: 0x0213, 0x74
    wr: 0x0214, 0x00
    wr: 0x0215, 0x00
    wr: 0x0218, 0x00
    wr: 0x0219, 0x00
    wr: 0x021A, 0x00
    wr: 0x021B, 0x10
    wr: 0x021C, 0x00
    wr: 0x021D, 0x40
    wr: 0x0220, 0x00
    wr: 0x0221, 0x00
    wr: 0x0222, 0x00
    wr: 0x0223, 0x10
    wr: 0x0224, 0x00
    wr: 0x0225, 0x80
    wr: 0x0228, 0x00
    wr: 0x0229, 0x00
    wr: 0x022A, 0x00
    wr: 0x022B, 0x10
    wr: 0x022C, 0x00
    wr: 0x022D, 0xC0
    wr: 0x0201, 0xFD
    wr: 0x0050, 0x06

    Then rdel is written and incremented mod 16 so the nest value will be used at the next attempt
    0x0032, rdel
    rdel = (rdel + 1) % 16

    Clear ADC alarms
    {
      rd: 0x030, tmp
      wr: 0x030, tmp | 0x30
      wr: 0x030, tmp & 0xCF
      rd: 0x205, tmp
      wr: 0x205, tmp | 0x18
    }

    Enable sysref receiver.
    wr: 0x0030, 0x00
    sleep 100 ms
    wr: 0x0030, 0x80
    sleep 100 ms
    wr: 0x0030, 0x40

    sleep 1 s
    Sysref is triggered here.
    sleep 2 s

    Wait until RX PLL is locked.

    Clear ADC alarms
    Clear JESD204B alarms on the FPGA
    sleep 1 s

    for (0 to 7):
    {
      Check for errors
      rd: 0x031, reg_0x031
      rd: 0x205, reg_0x205
      Clear ADC alarms

      if (((reg_0x031 & 0xC0) == 0x80) && ((reg_0x205 & 0x64) == 0x64) && (no JESD204 FPGA errors))
        success
      else
        sleep 1 s
    }

    goto beginning

  • Hi

    Sorry it's taken a while to analyze this and respond.

    I think the initial part of your writes are OK. I do think a few writes can be omitted as they are not necessary. 

    Specifically I would delete these two:

    wr: 0x002B, 0x13 - This register is reserved. This write was included in the early revision of the EVM GUI software but has no purpose now.

    wr: 0x0208, 0x07 - This write occurs twice. I would recommend deleting one of the writes.

    After that block of writes the SYSREF calibration sequence has a few items that I think are causing problems:

    See the highlighted items below:

    Then rdel is written and incremented mod 16 so the nest value will be used at the next attempt
    0x0032, rdel
    rdel = (rdel + 1) % 16

    Clear ADC alarms
    {
      rd: 0x030, tmp
      wr: 0x030, tmp | 0x30
      wr: 0x030, tmp & 0xCF
      rd: 0x205, tmp
      wr: 0x205, tmp | 0x18
    }

    Enable sysref receiver.
    wr: 0x0030, 0x00
    sleep 100 ms
    wr: 0x0030, 0x80 - This is setting SysRef_Rcvr_En, and leaving SysRef_Pr_En = 0. This is the recommended startup sequence.
    sleep 100 ms
    wr: 0x0030, 0x40 - If this is accurate, this write will enable the SysRef_Pr_En but at the same time is clearing SysRef_Rcvr_En. This will prevent SYSREF processing from working.

    sleep 1 s
    Sysref is triggered here. - If SYSREF is AC-coupled enabling SYSREF processing before starting SYSREF will definitely cause erroneous captures of SYSREF. When SYSREF is stopped and is AC-coupled the capacitors de-bias so that both SYSREFp and SYSREFn are at roughly the same voltage. In this condition any noise on the SYSREF inputs will cause false triggers of SYSREF.

    With AC-coupled SYSREF, the recommended sequence is to start SYSREF running continuously, then enable SYSREF receiver and SYSREF processing, then clear the error flag bits. Then check the status bits again at the first RDEL setting. SYSREF processing should be disabled before changing the RDEL setting and then re-enabled after the new value is set. Then at each RDEL setting the SysRefDet and Dirty Capture bits should be checked.

    sleep 2 s

    Wait until RX PLL is locked. - It isn't really necessary to bring up the link on the FPGA side during the SYSREF RDEL calibration sequence. Once the final RDEL setting is chosen and the ADC has been synchronized to SYSREF the RX side can be enabled.

    Clear ADC alarms
    Clear JESD204B alarms on the FPGA
    sleep 1 s

    for (0 to 7):
    {
      Check for errors
      rd: 0x031, reg_0x031
      rd: 0x205, reg_0x205
      Clear ADC alarms

      if (((reg_0x031 & 0xC0) == 0x80) && ((reg_0x205 & 0x64) == 0x64) && (no JESD204 FPGA errors))
        success
      else
        sleep 1 s
    }

    goto beginning

    I hope this is helpful.

    Best regards,

    Jim B

  • Thank you for spotting my silly mistake. Changing wr: 0x0030, 0x40 to wr: 0x0030, 0xC0 makes it detect sysref without dirty capture when using a continuously running sysref. I now have deterministic latency between startups. Thank you for your help.