I am trying to make the ADC12J1600 work with deterministic latency between startups. A pulsed sysref with the frequency of 12.5 MHz (1/128 of the device clock) is used. That frequency is a sub harmonic of the LMFC. I have also tried a continuous sysref. The JESD204B link start up and the FPGA receives data from the ADC, but the values of the RBD count for each start up seams to be random and span the whole range from 1 to 32. I can also observe this random latency in my data. Also the Dirty Capture (bit 7) is set to high and the SysRefDet (bit 6) is set to low in register CLKGEN_1 (0x031). According to the documentation this indicates that setup or hold is not met for SYSREF. I have tried to cycle through all the different delays of SYSREF by using RDEL (3-0) in register CLKGEN_2 (0x032). I have also tried to add some external delay to either the SYSREF or device clock combined with RDEL. The result are always the same, Dirty Capture is high, SysRefDet is low and RBD count is random. Do you have any suggestions of what may be wrong or how to further investigate to problem?
We use the following settings: L=1, M=2, F=4, N=15, N'=16, S=1, K=32, DDR=0, P54=1
Decimation = 32. Device clock is 1600MHz. Sysref 12.5MHz pulsed or continuous.