ADS8684: Sample Source Code for ADS8688 ADC

Hello User5786552,

Welcome to E2E forum.

Unfortunately, we do not have the code you want. To communicate with ADC, please follow the timing requirements in below timing diagram from ADS8684 datasheet. There is a detailed example in Figure 72 and page 34 of datasheet including explanation about the timing. Please notice that ADS8684 will latch the data on the SDI line into the device on every falling edge of SCLK, also the conversion data is output  on the SDO line  at the falling edge of SCLK by ADC, your host controller should read the data at next falling edge of SCLK.

Please let me know if you have any question about ADS8684, thanks.

Best regards

Dale

Hi Dale,

Thank you very much for your reply. 

I have some questions about the ads8684.

What is the correct power up sequencing linked with timing requirements. I know this information is in the datasheet but I don't understand the order in which to proceed. Could you help me ?

Regards

Marc

Hi Marc,
There is no specific power sequencing for ADS8684, AVDD and DVDD can be set independently. an attention should be taken only for below:
1. DVDD on ADC should be available before digital input signal(SCLK,SDI,/CS etc.) because the signal on digital inputs are limited to -0.3~DVDD+0.3V.
2. The voltage potential between GND and REFGND should be limited between -0.3V to 0.3V.
3. Check Absolute Maximum Ratings for other limits.
Thanks.

Best regards
Dale

please send the sample code for ADS8588S with parallel connection.
main id -> npnamratapatil93@gmail.com

Hello Namrata,
Thanks for your query on E2E. Unfortunately, we didn't release a sample code for ADS8588S, but I will be happy to support you for your any questions about this ADC. Thanks.

Best regards
Dale