ADS7951: analog I/P setting after chan cahnge and acquisition phase

Hi Xiaoqing

SAR ADCs have internal sample and hold capacitor which needs to be charged to input voltage when input switch is closed. The term acquisition phase is referred to time window given to acquire input signal and charge this capacitor to (Input signal -1/2LSB) value. Datasheet mentions the minimum value of the acquisition time that has to be met when operating device at full throughput.

To meet the datasheet performance numbers it is necessary for external driver circuit to settle to ( input voltage -1/2LSB) value within given acquisition time. The settling at the ADC input depends on number of parameters such as driver amplifier, R-C filter values, ADC acquisition time etc.

To know more about ADC input driver circuit and settling behavior, please refer to TI Precision LABs for ADCs.
training.ti.com/ti-precision-labs-adcs

Thanks & Regards
Abhijeet

Hi Abhijeet,

Thanks for your reply, and I have another question, as shown in below picture, what is the SDO data on frame1 and frame2, are they random? if frame1 is the first time for sampling.

Thanks!