Hello,
I have a question about using OR pin as DCLK2.
My ADC08D1520 is connected to an ARRIA10 FPGA which has 48 pin banks. For this reason DI, DId and DCLK are connected to bank X while DQ, DQd and DCLK2/OR are connected to bank Y. This means I must configure OR pin to work as DCLK2.
Now, the FPGA acquire data through I/O serdes which need initial synchronization, for this I'm going to use the ADC test pattern, and here's the question! As I can see from the datasheet the test pattern makes OR pin doing 01010010100... My question is: if I use the test pattern generaton while OR is configured as DCLK2, during test pattern this pin still works as DCLK2 or not?
Because if it isn't I shall change strategy due to the impossibility to synchronize serdes on DQ and DQd.
Thank you
