ADS54J60: How to use the interleave correction circuit of ADS54J60

I directed your question to a device expert and they should be back with you shortly.

Thanks

Yusuf

Dear Sir,

Thank you for your reply. I'm looking forward to the feedback.

BTW, I found some resister settings of interleave status in other thread of E2E,

and then tested.

I encountered strange phenomena for FFT spectrum on ADS54J60.

Attached figures please confirm the amount of distortion.

・Default (without any additional resister setting)

・Freeze Interleave Engine

Following SPI sequence is referenced from a related tread.

-------------------------------------------------

0x4005 0x01  // Enable single channel writes

0x4004 0x61

0x4003 0x00

0x4002 0x05

0x4001 0x00

0x6078 0x00 // For CH-A

0x7078 0x00 // For CH-B

0x4004 0x68

0x4003 0x00

0x4002 0x00

0x4001 0x00

0x604D 0x01 // For CH-A

0x704D 0x01 // For CH-B

0x6068 0x04 // For CH-A

0x7068 0x04 // For CH-B

-------------------------------------------------

The distortion of multi tone has been reduced when interleave engine froze.

But JESD204 link was disconnected without a return to unfreeze state immediately.

From this phenomena, ADC interleave mismatch is strongly suspected for the distortion.

I would like to get your feedback about this issue.

For your reference, other information show as below.

・ADS54J60 is mounted on our custom board.

・Input signal is generated AWG instrument. This signal has no significant distortion.

・ADC distortion for multi tone becomes worse as input power increase.

・SNR of single tone is around 60dB at 420MHz. It will be reasonable.

Regards,

ADS54J60_Fs_by_4_Correction_Cust_9_4_18.docUser,

Some of the register settings you used where wrong. Please see the attached document which will be added to the future release of the data sheet.

Regards,

Jim

Dear Jim,

Thank you for your reply. 

I'v been confirmed the settings of  Fs/4-Spur correction module.

However, Fs/4-Spur correction is absolutely no relation to my issue.

The resister settings which I previously posted are copied from the attached document.

I found this file in  https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/600466

Could you explain the function of "IL Engine" in this document?

0246.ADS54J60_DC_IL_register_info.doc

Regards,

Dear Jim,

The following resister setting has strong influence for Multitone Power Ratio.

------------------

0x4004 0x68

0x4003 0x00

0x4002 0x00

0x4001 0x00

0x604D 0x01         // Must wirite 0 in datasheet. But I modified.

0x6068 0x04         // There is no information in datasheet.

------------------

・Before set above resister (Default)

・After set above resisters

I'd like to get more information for  the role of hidden resisters.

Could you please explain "IL Engine" and provide information for hidden resisters?

Regards,

User,

May I ask why do you need this information? What is your end product and how would this information benefit you?

Regards,

Jim

Hi,

Our team is in charge of  develop a precision digitizing instrument.

We selected ADS54J60 as main IC in this instrument.

However the performance of Mintitone Power Ratio does not meet our requirement as I reported before.

If there is no way to improve the performance of ADS54J60,

we should give up to use ADS54J60, and then we should find an alternative ADC from other company.

First of all, I want to know the root cause of the phenomenon that is occurring.

Then I would like to investigate ways to improve it.

That's why I asked with our confidential measured data.

Regards,

 

User,

The Interleaving engine works on correcting timing and gain mismatch between the ADC cores.

Exercising Freeze would freeze this correction. When you are increasing amplitude, at what value is the ADC power?

 

Regards,

 

Jim

Hi,

# Measure sequence
No signal => Initialize ADC => Signal ON => ADC data captured by Integrated Logic Analyzer IP in FPGA
# Input Signal Power
from -10dBm to 0dBm
# Defect phenomenon
No distortion occurred at input signal band of 0-200MHz,
Multitone distortion occurred at input signal band of 0-400MHz.

Regards,

User,

Can you back off on the input power so it does not go above -1dBFs. This is the max power all data sheet measurements are taken at. What is the spacing of your multitones? Do you see this issue with a larger spacing?

Regards,

Jim   

Hi, Jim

I know -1dBFs is the max power for ADS54J60.
Even if input signal is increased 0dBm, peak power is far from -1dBFs.
Peak-to-Average power Ratio(PAR) of our multitone signal is adjusted from 11.5dB to 16.5dB.
But the distortion issue is not depended on PAR.

The spacing of Multitone is 52kHz.
It is the same for both 0-200MHz and 0-400MHz, but the number of carrier is double.

Regards,

Hi,

Could you please feedback for this issue?
It is urgent for me.
Once again, I want to know the root cause of the phenomenon that is occurring by hidden resisters.

Regards,

Feature Update and IL freeze instructions.docxUser,

The only adjustments for the IL engine is to freeze it, unfreeze it, or bypass it per the instructions attached. Have you tried all three? When freezing the engine, make sure to reset the digital core first and wait 2ms. There also was a feature update added to the register map. See if this register write helps. Have you tried freezing offset correction to see what effect this has with your setup?

Regards,

Jim

 

Hi,

Thank you for providing the document.

I've been tested IL freeze setting by following the document.

JESD204 link is more stable than before.
IL engine freeze seems to be effective to improve the distortion.

In addition, both IL bypass and DC offset freeze have been measured.
  IL bypass :  Quite poor performance for Multitone Power Ratio
  DC offset freeze : No relation to this issue

I'd like to find the root cause of this phenomenon,
but that doesn't ring a bell.
Have you ever encountered such a problem before?

Our board is employed transformer-coulpled circuit in datasheet
for the input drive circuit.

Regards,