DDC114 Questions

Danny,

                   1. DCLK must be the continuous 80 bits for 4 channel (fomat=high)? Can we use the separated 20 bits DCLK for 4 channel (That will exist delay time for ch4 to ch1)?  Do you mean that you want to read out 20 bits for channel 4, pause, 20 bits for channel 3, pause, ... 20 bits for channel 1?  If so then I can say there will not be a problem functionally with this - internally it is just a Parallel-Load-Serial-Output shift register.  If possible keep the DCLK synchronized and stable to reduce potential digital coupling noise that could reduce the performance.

                   2. Photodiode (S1336-5BQ, hamamatsu) is used in our design and should we ground the device to DDC114?I connect the AGND and DGND to the same plane (refer the layout from datasheet).  Anything attached to the Analog Inputs of the DDC114 should be referenced to AGND.  While I am not an expert in photodiodes, I suspect this is the case.

                   3. We use MCU-SPI to control DDC114 and should I use the DCK-falling edge to strobe data?  From Page 21, Figure 20 of the DDC114 data sheet - the DOUT changes on the falling edge of DCLK, but t21 shows there is 5ns of hold time, so strobing the data on the falling edge of DCLK is likely to work just fine as long as it is within 5ns.

                   4. DDC 4Mhz clk should come from the MCU? I used independent oscillator instead of it.  To best synchronize the device and provide accurate timing, yes, the 4MHz CLK should come from the MCU or come from the clock source that drives the MCU or a divider of what drives the MCU. 

                   5. We send the continuous 30hz CONV to DDC114 and observe the DATAVALID and then capture the DOUT via MCU-SPI. Is the experiment exact or not?  This is in alignment with the intended operating mode of the device, yes.

 I hope this has helped,

Jason