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DAC5681Z: Latency Issue

Bahadır Dönmez
Prodigy 20 points
Part Number: DAC5681Z


Hello,

We are using in our lab the FMC110 Card of Abaco, which has two DAC5681Z chips on it. We are currently working on the implementation of a quantum feedback system where we use the VC707 FPGA Board together with the ADC and the DAC chips on the FMC110 Card.
Our current experiments require a very low latency for DAC Chips. When we tested the DAC interface, we observed a latency of around 78 ns only for DAC chip. This is very close to the "Digital Latency + Output propagation delay = 78.5ns" as it is stated on the Page 9 of the DAC5681Z Datasheet. In addition, we have some additional latency caused by FPGA firmware to set DAC signal values. Nevertheless, we focus only on reducing the latency of DAC chip by ignoring the latency of FPGA firmware.    
My question is that, if it is somehow possible to reduce this latency (78 ns) of the DAC chip?
When we investigated the datasheet of DAC5681Z, we have seen on Page 33  that it takes at least 50 clock cycles to set clkdiv_sync signal, therefore we thought there might be a default latency to synchronize multiple DAC devices. We thought, if we disable the Syncronization of the DAC chips we may reach lower latency. 
In Functional Block Diagram Figure at Page 17 of the datasheet, we have seen that there is "FIFO Sync Disable" signal from Sync & Control module. We thought we should disable the Syncronization with this property (FIFO Sync Disable) of DAC5681Z. We have checked the Register Map on Page 39 of DAC5681Z Datasheet but we could not find any option to disable the synchronization. Then we found the Revision D version of the datasheet  and we saw there that BIT 4 of the CONFIG5 register is named "FIFO_sync _dis". This bit is shown as "reserved" in the latest datasheet and is set to 0 in the default reference firmware of Abaco. So, we tried to set this bit to 1. However, the DAC chip stopped working. Therefore we needed to set it back to 0.
Briefly, my questions are: 
* Do you know if the synchronization of the two DAC chips on the FMC110 card is enabled by default ? 
* How could we disable the synchronization to reduce the latency of DAC Chips?
* Do you have another idea to reduce the latency of DAC chip ?
Looking forward to hearing your answer.
Thank you very much in advance.
Kind regards,
  • 0
    TI__Guru* 91947 points

    User,

    We are looking into this.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 20 points

    Thank you very much.

    I am looking forward to hearing your recommendations on how we can reduce the latency of the DAC chip.

    Since we do not need the two channels to be synchronized, if disabling the synchronization decreases the latency we would like to decrease it,

    Kind regards.

  • 0
    TI__Mastermind 20541 points
    Hi

    Even when you are not synchronizing two DACs together and just using a single DAC there is delay from the time the DATA is sampled to when output is updated. There is 2.5ns of analog propagation delay + 76(digital delay) DAC clock cycle delay(depending on sample clock) when no interpolation is used. However when using 2X interpolation the digital delay is 158 DAC clock cycle and 289 clock cycles with 4X interpolation.

    The only way to reduce the digital delay is to not use interpolation or use higher clock sampling clock rate.

    Regards,
    Neeraj