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AFE5809: trigger signal

Part Number: AFE5809

hi,

dose afe5809 needs a trigger signal, either an external trigger event through the TX_SYNC_IN pin or a manual trigger event through Register 0[2] , for each sample? or we just have to trigger it once and the data will come out in burst mode.

I have made a custom board, where the AFE5809 is controlled by a spartan 6 FPGA, the ADC CLK is supplied by the FPGA and is 20MHz. Currently i just want to see ADC sampled data, so I config adc registers as follow:

 

ADDR[0x]

BIT

Value

Discription

1

0

0

1

Resets the device and self-clears the bit to 0. Note: Register 0 is a write only register.

2

16

0

1

Digital demodulator is disabled

3

1

15

1

Single-ended clock input

4

2

15:13

111

Ramp TEST_PATTERN_MODES

5

4

4

1

1: MSB first

after that, i write 1 to demod Register 0[2]

I can get 140MHz DCLK, but I cann't get FCLK and DOUT.

then i generate a 10MHz clk to the TX_SYNC_IN pin, but still cann't get FCLK and DOUT.

thank you!