ADS127L01: Clock tree design for SCLK and CLK

[FAE] Andrew Wang

Part Number: ADS127L01

Hi Team,

For ADS127L01 best clock design practice, we suggest to have same source of SCLK and CLK in our datasheet.

We understand this is for intermodulation problem minimize.

Customer is asking if frequency btw SCLK and CLK difference is the major problem to intermodulation, or the phase difference, correct?

Also, from our ADS127L01 EVM design, it seems SCLK and CLK are not same source, is reason we didn't use same clock source?

Any TI Reference design schematics we use same clock source for clock tree, can I know about it?

Thanks.

Andrew

over 7 years ago

0 Tom Hendrick over 7 years ago

TI__Guru**** 182091 points

Hi Andrew,

Please review section 5.6 of the ADS127L01EVM User's Guide. The 16MHz clock feeds both the TIVA processor and the ADS127L01, so they are same source. The DFF's on board can scale down the clock to the ADS127L01, but they are still synchronous to each other which is the key to best performance.

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ADS127L01: Clock tree design for SCLK and CLK