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ADS1118-Q1: Communication during data ready

RYO
Intellectual 2000 points
Part Number: ADS1118-Q1
Other Parts Discussed in Thread: ADS1218, ADS1118

Hello all,

Thank you for your support always. I would like to know what happens when the data is written/read during /DRDY is low. Will the pin remain low after communication is done? Or will it be back to High state until the next conversion is done?

Best regards,
RYO

  • 0
    TI__Guru* 97465 points

    RYO,


    If you go into the ADS1218 datasheet, look at Figures 40, 41, and 42, you can see the behavior of the DOUT/DRDY pin after clocking out data.

    If you clock out the just the conversion data as shown in Figure 42, the DOUT/DRDY will retain the value of the last output bit, staying either high or low. If you use the 32-bit data transmission cycle, the DOUT/DRDY will go high at the end (when the CONFIG register is read). The only exception is if a new data conversion comes in during the read of the 32 bits. If a new conversion comes in during the the read of the data and CONFIG register, then the status of the DOUT/DRDY after the read may be high or low (and the output of the read may be corrupted).

    Much of the time, we recommend single-shot conversion for this device to ensure there is no data corruption.


    Joseph Wu

  • 0 in reply to Joseph Wu
    TI__Intellectual 2000 points

    Thank you, Joseph.

    I have one more question. Will the CONFIG register be written correctly when the CONFIG is written during AD conversion is finished? Or will the CONFIG data before AD finishes be corrupted?

    Best regards,
    RYO

  • 0 in reply to RYO
    TI__Guru* 97465 points
    RYO,


    When the CONFIG register is written, the ADS1118 will finish the conversion in progress. The changes written to the CONFIG register do not take place until after the conversion completes. This means you should be able to correctly read the previous conversion.


    Joseph Wu