Hi,
I am using ADC34j45EVM with xilinix's FPGA kcu105.
I connected clocks like the followings:
jesd coreclock: CLK_LA0_0P/M (ADC34j45EVM) ------> rx_core_clk: glblclkp/n (Xilinx's JESD ip core)
GTX_CLKP/M (ADC34j45EVM) -------> refclk: refclk0p/n (Xilinx's JESD ip core)
The received data of the physical core(jesd204_phy) are wrong (not "bcbcbcbc") and no right jesd sync.
So Please tell me if the clock connections are right? What are the possible reasons?
Best Regards,
Hong
Hi Hong,
After ensuring that the CLK_LA0 and GTX_CLK signals are enabled on the ADC34J45EVM (as shown in an earlier thread 
), you will need to ensure that the signals are going to the correct pins on the FMC connector of the KCU105.
Unfortunately, I do not have a firmware example using a Xilinx FPGA, but there are FPGA design files for our TSW14J56EVM capture card which uses and Altera (Intel) FPGA. This can be found under the Software section of this website
Furthermore, Xilinx has many resources available for assistance with using their devices. Here is one forum page that might be helpful.
Hope that helps.
Best Regards,
Dan
