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Original question:

ADS131A04: Problem getting data from 2nd device in ADS131A04 SPI chain.

ADS131A04: can you bypass the internal clock dividers?

Arthur Dent
Prodigy 230 points
Part Number: ADS131A04

Hi,

Prior to incorporating the design into a pcb i interpreted the datasheet to allow a base clock in (fclkin) while not enabling either CLKin divider ratio nor the iCLK divider ratio.

My thinking was that by leaving those bits to 000 for both i would in effect maintain the base clock (fclkin) through the dividers such that fclkin=fiCLK=fmod=4Mhz.

What i have found is that the resulting fdata rate from this configuration results in 1/4th what one would expect with a 4Mhz fmod clock.

It seems that even the registers allow a 000 3 bit divisor configuration, which i thought would allow for a divide by 1 situation..it actually divides by 2 through each 3 bit divisor.

Experiment Example :

fclkin=4Mhz. set CLK1 register=0x00 set CLK2 register=0x0f (in my interpretation both dividers were set to 1) ....resulting fdata=31250Hz.

same settings

fclkin=16Mhz fdata=125000Hz as data sheet indicates.

Is there any reserved undocumented trick that would allow me to set the divisors both to 1 and maintain my 4Mhz input clock?

thanks

  • 0
    TI__Guru 66256 points

    Hi Arthur,

    Thank you for your post!

    The "Reserved" bit field settings are not meant to be used. There is no trick to bypassing the internal clock dividers. The only exception is when the device is operating in Synchronous Slave Mode, in which case the SCLK can be used as ICLK as well.

    Can you tell us more about what you're trying to do? Why can you not use a 16-MHz input clock frequency and set the dividers to the minimum " / 2" setting?

    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 230 points

    Hi Ryan,

    I wanted to be able to pass thru a 4Mhz clock without enabling the dividers is what i am trying to do. It is not that i can not use a 16Mhz clock, it is more along the line of i have built and populated a clock board providing 4MHz inputs. Given that the end fmod clock is okay at 4MHz, it did not seem an issue to me to simply not enable the dividers (or bypass them).  The answer you gave confirms that the internal pathways will always be divided by 2 regardless whether the 3bit divisors have a bit set  for the divisor entries.

    If you have to put some notes on a case, i would offer the following.

    "The end user would appreciate that the situation above be described in a foot note on the divisor page where a value other than 0b000 must be used for the divisor entry.

    If not then well i tried :-)

    I appreciate the reply.

    Thanks