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DAC37J84EVM: DAC37J84EVM Output issue

Swarup Putti
Prodigy 100 points

Part Number: DAC37J84EVM
Other Parts Discussed in Thread: LMK04828

Hi,

I want to generate i & q signals from all 4 channels of  DAC37J84EVM with Xilinx FPGA through FMC connector. I check JESD204B from FPGA side its working fine.

Clk & SYSREF are configured from LMK04828 and its working fine, but i am not getting output from DAC channel. Pls find & check the attached configuration screenshots of DAC.

Suggest me where i should do mistake.

Thanks & Regards,

Swarup.DAC37J84EVM Output issue.docx

  • 0
    TI__Genius 9695 points
    Hi Swarup,

    Some Xilinx FPGAs require 2 reference clocks so you may have to enable CLK12 of LMK04828. There is a reference design at the link below you can refer to:
    www.ti.com/.../slac690

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 100 points

    Hi Eben,

    Our Xilinx FPGA just requries only one Ref clock and that is coming properly that's why we are able to achieve sync and sysref in jesd ips status also. Regarding to waveform we are clearly seeing that whatever the waveform loaded in PS is coming to FPGA and we are able to see in chipscope also on AWG output.
    Is there anything else which i need to follow.
    Regards,
    Swarup.

  • 0 in reply to Swarup Putti
    TI__Genius 9695 points
    Hi Swarup,

    Try the following:
    1) Are there any alarms reported when you read back the alarms from the 'Alarms and Errors' tab in GUI?
    2) Check that TXENABLE pin is set to Low
    3) While SYSREF is present, toggle the JESD init state on and off. You can do this from the JESD Block tab of GUI. Check and confirm that SYNC toggles to Low and back to High.

    Thanks,
    Eben.